APA (7th ed.) Citation

Hew, K. Y. (2008). Verilog design of bist on AES256 processor core with FPGA implementation.

Chicago Style (17th ed.) Citation

Hew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.

MLA (8th ed.) Citation

Hew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.

Warning: These citations may not always be 100% accurate.