APA引文

Hew, K. Y. (2008). Verilog design of bist on AES256 processor core with FPGA implementation.

Chicago Style (17th ed.) Citation

Hew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.

MLA引文

Hew, Kean Yung. Verilog Design of Bist on AES256 Processor Core with FPGA Implementation. 2008.

警告：这些引文格式不一定是100％准确.