Verilog design of bist on AES256 processor core with FPGA implementation

Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to...

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Main Author:	Hew, Kean Yung
Format:	Thesis
Language:	English
Published:	2008
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/18136/1/HewKeanYungMFKE2008.pdf
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id	my-utm-ep.18136
record_format	uketd_dc
spelling	my-utm-ep.181362018-07-23T05:45:49Z Verilog design of bist on AES256 processor core with FPGA implementation 2008-10 Hew, Kean Yung TK Electrical engineering. Electronics Nuclear engineering Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to protect data and ensure privacy. Hence, AES hardware cannot afford any encryption failure which will corrupt the whole system. Built-In-Self-Test (BIST) introduced into the AES system will increase the system testability and reliability, which in turn will protect the system from attack and will incur less testing cost. This project aims to continue previous UTM student’s research on FPGA implementation of AES system in System-on-Chip (SoC) design. By extending further, a proposed AES hardware BIST design is incorporated into the AES processor core in Verilog RTL and FGPA implementation. This will be a valuable asset to UTM for future SoC researches on AES and BIST design. 2008-10 Thesis http://eprints.utm.my/id/eprint/18136/ http://eprints.utm.my/id/eprint/18136/1/HewKeanYungMFKE2008.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Hew, Kean Yung Verilog design of bist on AES256 processor core with FPGA implementation
description	Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to protect data and ensure privacy. Hence, AES hardware cannot afford any encryption failure which will corrupt the whole system. Built-In-Self-Test (BIST) introduced into the AES system will increase the system testability and reliability, which in turn will protect the system from attack and will incur less testing cost. This project aims to continue previous UTM student’s research on FPGA implementation of AES system in System-on-Chip (SoC) design. By extending further, a proposed AES hardware BIST design is incorporated into the AES processor core in Verilog RTL and FGPA implementation. This will be a valuable asset to UTM for future SoC researches on AES and BIST design.
format	Thesis
qualification_level	Master's degree
author	Hew, Kean Yung
author_facet	Hew, Kean Yung
author_sort	Hew, Kean Yung
title	Verilog design of bist on AES256 processor core with FPGA implementation
title_short	Verilog design of bist on AES256 processor core with FPGA implementation
title_full	Verilog design of bist on AES256 processor core with FPGA implementation
title_fullStr	Verilog design of bist on AES256 processor core with FPGA implementation
title_full_unstemmed	Verilog design of bist on AES256 processor core with FPGA implementation
title_sort	verilog design of bist on aes256 processor core with fpga implementation
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2008
url	http://eprints.utm.my/id/eprint/18136/1/HewKeanYungMFKE2008.pdf
_version_	1747815201448656896

Verilog design of bist on AES256 processor core with FPGA implementation

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