A hardware architecture of prewitt edge detection
The objective of this project is to develop a real-time hardware architecture for Prewitt edge detection algorithm. Prewitt edge detection provides differencing operation in the single kernel. Verilog hardware description language was used as the hardware programming language for a real-time edge de...
Saved in:
主要作者: | Seif, Aramesh |
---|---|
格式: | Thesis |
語言: | English |
出版: |
2009
|
主題: | |
在線閱讀: | http://eprints.utm.my/id/eprint/18328/1/ArameshSeifMFKE2009.pdf |
標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
相似書籍
-
A hardware architecture of gaussian filter for digital image processing
由: Mohammadpoursalut, Mohammad
出版: (2009) -
A hardware architecture of stateless open digest spam fingerprinting unit
由: Monemi, Alireza
出版: (2010) -
Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
由: Oh, Eng Wei
出版: (2015) -
Electrocardiogram QRS detection hardware accelerator for ASIC implementation
由: Lim, Zhi Qing
出版: (2020) -
Hardware implementation of naive bayes classifier for malware detection
由: Al Hussein, Yahya Khaled
出版: (2021)