System-on-chip (SoC) testing using adhoc high-level design for-testability method
The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to ma...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/18577/1/ChengChenKongMFKE2009.pdf |
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| Summary: | The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to make the chip more easily testable. By increasing the DFT features into a chip, this will definitely increase the overhead of the chip. In this project, an alternative DFT method is used to minimize the overhead of the chip resulted from DFT without affecting the fault coverage. A case study is conducted by applying the proposal ad-hoc DFT method on GCD calculator. Area overhead and test application clock cycles are evaluated and compared to those parameters resulted from the conventional DFT method called full scan. The case study showed that the area overhead was smaller and the test application clock cycles were less when GCD was augmented with proposed DFT method. |
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