System-on-chip (SoC) testing using adhoc high-level design for-testability method
The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to ma...
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| التنسيق: | أطروحة |
| اللغة: | English |
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2009
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| الوصول للمادة أونلاين: | http://eprints.utm.my/id/eprint/18577/1/ChengChenKongMFKE2009.pdf |
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my-utm-ep.185772018-06-25T09:02:14Z System-on-chip (SoC) testing using adhoc high-level design for-testability method 2009 Cheng, Chen Kong TK Electrical engineering. Electronics Nuclear engineering The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to make the chip more easily testable. By increasing the DFT features into a chip, this will definitely increase the overhead of the chip. In this project, an alternative DFT method is used to minimize the overhead of the chip resulted from DFT without affecting the fault coverage. A case study is conducted by applying the proposal ad-hoc DFT method on GCD calculator. Area overhead and test application clock cycles are evaluated and compared to those parameters resulted from the conventional DFT method called full scan. The case study showed that the area overhead was smaller and the test application clock cycles were less when GCD was augmented with proposed DFT method. 2009 Thesis http://eprints.utm.my/id/eprint/18577/ http://eprints.utm.my/id/eprint/18577/1/ChengChenKongMFKE2009.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering |
| institution |
Universiti Teknologi Malaysia |
| collection |
UTM Institutional Repository |
| language |
English |
| topic |
TK Electrical engineering Electronics Nuclear engineering |
| spellingShingle |
TK Electrical engineering Electronics Nuclear engineering Cheng, Chen Kong System-on-chip (SoC) testing using adhoc high-level design for-testability method |
| description |
The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to make the chip more easily testable. By increasing the DFT features into a chip, this will definitely increase the overhead of the chip. In this project, an alternative DFT method is used to minimize the overhead of the chip resulted from DFT without affecting the fault coverage. A case study is conducted by applying the proposal ad-hoc DFT method on GCD calculator. Area overhead and test application clock cycles are evaluated and compared to those parameters resulted from the conventional DFT method called full scan. The case study showed that the area overhead was smaller and the test application clock cycles were less when GCD was augmented with proposed DFT method. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Cheng, Chen Kong |
| author_facet |
Cheng, Chen Kong |
| author_sort |
Cheng, Chen Kong |
| title |
System-on-chip (SoC) testing using adhoc high-level design for-testability method |
| title_short |
System-on-chip (SoC) testing using adhoc high-level design for-testability method |
| title_full |
System-on-chip (SoC) testing using adhoc high-level design for-testability method |
| title_fullStr |
System-on-chip (SoC) testing using adhoc high-level design for-testability method |
| title_full_unstemmed |
System-on-chip (SoC) testing using adhoc high-level design for-testability method |
| title_sort |
system-on-chip (soc) testing using adhoc high-level design for-testability method |
| granting_institution |
Universiti Teknologi Malaysia, Faculty of Electrical Engineering |
| granting_department |
Faculty of Electrical Engineering |
| publishDate |
2009 |
| url |
http://eprints.utm.my/id/eprint/18577/1/ChengChenKongMFKE2009.pdf |
| _version_ |
1747815309220249600 |