System-on-chip (SoC) testing using adhoc high-level design for-testability method
The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to ma...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 語言: | English |
| 出版: |
2009
|
| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/18577/1/ChengChenKongMFKE2009.pdf |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|