Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation

Cryptographic applications becoming increasingly more important in todayâ€™s world of data exchange. Big volume data needs to be transferred from one location to another through communication path but exposes to attackers. Cryptography services are essential in order to provide the authentication, p...

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Main Author:	Ismail, Mohd. Izuan
Format:	Thesis
Language:	English
Published:	2006
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/2195/1/MohdIzuanIsmailMFKE2006.pdf
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spelling	my-utm-ep.21952018-06-13T07:07:49Z Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation 2006-07 Ismail, Mohd. Izuan TK Electrical engineering. Electronics Nuclear engineering Cryptographic applications becoming increasingly more important in todayâ€™s world of data exchange. Big volume data needs to be transferred from one location to another through communication path but exposes to attackers. Cryptography services are essential in order to provide the authentication, privacy, non-repudiation and integrity of private data being transmitted. System-on-Chip (SoC) technology enters the mainstream in digital design. The advances in reconfigurable hardware create the possibility of developing a microchip with application-specific processors. The processors perform their respective dedicated algorithm-intensive computations. This thesis presents the architecture for implementation of the new Advanced Encryption Standard (AES) in hardware for operating under SoC environment. The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). The processor design is completely described in hardware description language, VHDL. When designing hardware, the desire is often to achieve the highest performance possible. With implementation on Alteraâ€™s APEX FPGA, experimental evaluation of the AES Crypto-Processor running at 50 MHz using test vector provided in FIPS (2002) yields an average encryption rate at 188.24 Mb/s and decryption rate at 200 Mb/s which makes the overall performance is at 192.12 Mb/s. The design uses only 3,355 logic elements or 31% of hardware resources. The result of this work is the first step to the ultimate goal of developing a complete cryptographic system processor for security application in embedded system design 2006-07 Thesis http://eprints.utm.my/id/eprint/2195/ http://eprints.utm.my/id/eprint/2195/1/MohdIzuanIsmailMFKE2006.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Ismail, Mohd. Izuan Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
description	Cryptographic applications becoming increasingly more important in todayâ€™s world of data exchange. Big volume data needs to be transferred from one location to another through communication path but exposes to attackers. Cryptography services are essential in order to provide the authentication, privacy, non-repudiation and integrity of private data being transmitted. System-on-Chip (SoC) technology enters the mainstream in digital design. The advances in reconfigurable hardware create the possibility of developing a microchip with application-specific processors. The processors perform their respective dedicated algorithm-intensive computations. This thesis presents the architecture for implementation of the new Advanced Encryption Standard (AES) in hardware for operating under SoC environment. The proposed AES Crypto-Processor accelerates the AES algorithm in reconfigurable Field Programmable Gate Arrays (FPGA). The processor design is completely described in hardware description language, VHDL. When designing hardware, the desire is often to achieve the highest performance possible. With implementation on Alteraâ€™s APEX FPGA, experimental evaluation of the AES Crypto-Processor running at 50 MHz using test vector provided in FIPS (2002) yields an average encryption rate at 188.24 Mb/s and decryption rate at 200 Mb/s which makes the overall performance is at 192.12 Mb/s. The design uses only 3,355 logic elements or 31% of hardware resources. The result of this work is the first step to the ultimate goal of developing a complete cryptographic system processor for security application in embedded system design
format	Thesis
qualification_level	Master's degree
author	Ismail, Mohd. Izuan
author_facet	Ismail, Mohd. Izuan
author_sort	Ismail, Mohd. Izuan
title	Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
title_short	Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
title_full	Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
title_fullStr	Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
title_full_unstemmed	Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
title_sort	design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2006
url	http://eprints.utm.my/id/eprint/2195/1/MohdIzuanIsmailMFKE2006.pdf
_version_	1747814405387583488

Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation

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