USB soft core with altera Nios processor

This objectives of this project learning the process of implementing an System-on-Chip (SoC) using the Altera development board. The chosen board is the Excalibur board which consists of the APEX 20KE200 FPGA. Besides this, Quartus II software is needed as the platform for the development of this pr...

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Bibliographic Details
Main Author:	Cheah, Chee Teong
Format:	Thesis
Language:	English
Published:	2007
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/263/1/CheahCheeTeongMFKE2007.pdf
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id	my-utm-ep.263
record_format	uketd_dc
spelling	my-utm-ep.2632018-02-19T06:56:33Z USB soft core with altera Nios processor 2007-11 Cheah, Chee Teong TK Electrical engineering. Electronics Nuclear engineering QA75 Electronic computers. Computer science This objectives of this project learning the process of implementing an System-on-Chip (SoC) using the Altera development board. The chosen board is the Excalibur board which consists of the APEX 20KE200 FPGA. Besides this, Quartus II software is needed as the platform for the development of this project. USB was used as example soft core component to be added to the SoC with the IP obtained from the Opencores web site. As the Nios the system uses the Avalon bus system, while the USB IP core is built for Wishbone bus system, a bridge which allows the both bus systems to communicate was required. This project succeeded in proving the functionality of the bridge. The USB core can either be programmed as Host or Slave. For the USB to communicate to the outside world, physical (PHY) layer circuit was required. The PHY chip used was the Fairchild USB1T11A. To build the PHY printed circuit board (PCB), the Santa Cruz connector located on the Altera development board was used. The PHY circuitry was built on a PCB which was then plugged into the Santa Cruz connector. The final task for the project was testing the USB driver. 2007-11 Thesis http://eprints.utm.my/id/eprint/263/ http://eprints.utm.my/id/eprint/263/1/CheahCheeTeongMFKE2007.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering TK Electrical engineering Electronics Nuclear engineering Cheah, Chee Teong USB soft core with altera Nios processor
description	This objectives of this project learning the process of implementing an System-on-Chip (SoC) using the Altera development board. The chosen board is the Excalibur board which consists of the APEX 20KE200 FPGA. Besides this, Quartus II software is needed as the platform for the development of this project. USB was used as example soft core component to be added to the SoC with the IP obtained from the Opencores web site. As the Nios the system uses the Avalon bus system, while the USB IP core is built for Wishbone bus system, a bridge which allows the both bus systems to communicate was required. This project succeeded in proving the functionality of the bridge. The USB core can either be programmed as Host or Slave. For the USB to communicate to the outside world, physical (PHY) layer circuit was required. The PHY chip used was the Fairchild USB1T11A. To build the PHY printed circuit board (PCB), the Santa Cruz connector located on the Altera development board was used. The PHY circuitry was built on a PCB which was then plugged into the Santa Cruz connector. The final task for the project was testing the USB driver.
format	Thesis
qualification_level	Master's degree
author	Cheah, Chee Teong
author_facet	Cheah, Chee Teong
author_sort	Cheah, Chee Teong
title	USB soft core with altera Nios processor
title_short	USB soft core with altera Nios processor
title_full	USB soft core with altera Nios processor
title_fullStr	USB soft core with altera Nios processor
title_full_unstemmed	USB soft core with altera Nios processor
title_sort	usb soft core with altera nios processor
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2007
url	http://eprints.utm.my/id/eprint/263/1/CheahCheeTeongMFKE2007.pdf
_version_	1747814351102803968

USB soft core with altera Nios processor

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