Network-on-chip non-preemptive test scheduling

Network-on-Chip (NoC) is an emerging design paradigm in complex system-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing scalability, and power dissipation, widespread interest in this novel paradigm is likely to grow. T...

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Main Author:	Mispan, Mohd. Syafiq
Format:	Thesis
Published:	2010
Subjects:	TK Electrical engineering Electronics Nuclear engineering
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id	my-utm-ep.26870
record_format	uketd_dc
spelling	my-utm-ep.268702017-08-15T00:30:45Z Network-on-chip non-preemptive test scheduling 2010 Mispan, Mohd. Syafiq TK Electrical engineering. Electronics Nuclear engineering Network-on-Chip (NoC) is an emerging design paradigm in complex system-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing scalability, and power dissipation, widespread interest in this novel paradigm is likely to grow. The reuse of on-chip network as test access mechanism has been proposed to handle the growing complexity for testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test scheduling methods are required to deliver feasible test time while meeting all the constraints. In this project, a new efficient test scheduling algorithm for NoCbased systems is proposed that can minimize the total test time. The proposed algorithm is more towards non-preemptive tests in terms of packet format by first considering the core that has biggest test time. The inherent parallelism within a NoC itself could be exploited to transport test data to IPs under test. The NoC switch and all interconnects are assumed fault free. This is to improve the efficiency by transporting test data on multiple paths and testing multiple NoC IPs concurrently. Experimental results for the ITC’02 SoC test benchmarks show that the nonpreemptive scheduling based on dedicated path able to give competitive results. 2010 Thesis http://eprints.utm.my/id/eprint/26870/ http://libraryopac.utm.my/client/en_AU/main/search/results?qu=Network-on-chip+non-preemptive+test+scheduling&te= masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Mispan, Mohd. Syafiq Network-on-chip non-preemptive test scheduling
description	Network-on-Chip (NoC) is an emerging design paradigm in complex system-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing scalability, and power dissipation, widespread interest in this novel paradigm is likely to grow. The reuse of on-chip network as test access mechanism has been proposed to handle the growing complexity for testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test scheduling methods are required to deliver feasible test time while meeting all the constraints. In this project, a new efficient test scheduling algorithm for NoCbased systems is proposed that can minimize the total test time. The proposed algorithm is more towards non-preemptive tests in terms of packet format by first considering the core that has biggest test time. The inherent parallelism within a NoC itself could be exploited to transport test data to IPs under test. The NoC switch and all interconnects are assumed fault free. This is to improve the efficiency by transporting test data on multiple paths and testing multiple NoC IPs concurrently. Experimental results for the ITC’02 SoC test benchmarks show that the nonpreemptive scheduling based on dedicated path able to give competitive results.
format	Thesis
qualification_level	Master's degree
author	Mispan, Mohd. Syafiq
author_facet	Mispan, Mohd. Syafiq
author_sort	Mispan, Mohd. Syafiq
title	Network-on-chip non-preemptive test scheduling
title_short	Network-on-chip non-preemptive test scheduling
title_full	Network-on-chip non-preemptive test scheduling
title_fullStr	Network-on-chip non-preemptive test scheduling
title_full_unstemmed	Network-on-chip non-preemptive test scheduling
title_sort	network-on-chip non-preemptive test scheduling
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2010
_version_	1747815530806378496

Network-on-chip non-preemptive test scheduling

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