Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm

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主要作者: Sua, Jia Pao
格式: Thesis
出版: 2010
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id my-utm-ep.26927
record_format uketd_dc
spelling my-utm-ep.269272012-08-02T08:31:38Z Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm 2010 Sua, Jia Pao Electrical Engineering TK Electrical engineering. Electronics Nuclear engineering 2010 Thesis http://eprints.utm.my/id/eprint/26927/ masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution Universiti Teknologi Malaysia
collection UTM Institutional Repository
topic Electrical Engineering
Electrical Engineering
spellingShingle Electrical Engineering
Electrical Engineering
Sua, Jia Pao
Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
description
format Thesis
qualification_level Master's degree
author Sua, Jia Pao
author_facet Sua, Jia Pao
author_sort Sua, Jia Pao
title Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
title_short Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
title_full Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
title_fullStr Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
title_full_unstemmed Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
title_sort power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
granting_institution Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department Faculty of Electrical Engineering
publishDate 2010
_version_ 1747815544698961920