Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm

Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Sua, Jia Pao
التنسيق:	أطروحة
منشور في:	2010
الموضوعات:	Electrical Engineering
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

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