VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm

As artificial neural networks continue to gain popularity in the domain of pattern recognition, there have been growing demands for these models to be executed at high-speeds. Thus, to cater to this need, the VLSI design and implementation of a neurohardware for high-speed pattern recognition is pro...

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Main Author:	Rajah, Avinash
Format:	Thesis
Language:	English
Published:	2005
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/2946/1/AvinashRajahMFKE2005.pdf
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id	my-utm-ep.2946
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spelling	my-utm-ep.29462018-06-25T00:42:56Z VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm 2005-12 Rajah, Avinash TK Electrical engineering. Electronics Nuclear engineering As artificial neural networks continue to gain popularity in the domain of pattern recognition, there have been growing demands for these models to be executed at high-speeds. Thus, to cater to this need, the VLSI design and implementation of a neurohardware for high-speed pattern recognition is proposed in this research. The UTM-Neuroprocessor implements the Kohonen Neural Network for pattern classification. High-speed pattern classification by the neural paradigm is achieved through massively parallel execution based on the neuron-parallel processing approach. For proof of concept purposes, a 10x10 UTM-Neuroprocessor, which implements a 10x10 Kohonen network, was developed in this work. The design and rapid FPGA prototyping of the neuroprocessor was achieved using VHDL and the Altera Nios embedded system development kit. The FPGA-based prototype of the 10x10 UTM-Neuroprocessor is able to function at a frequency of 100 MHz and delivers performances up to 5.079 GCPS and 2.285 GCUPS. Software components, including a VB-based GUI, were also developed to allow execution of pattern recognition applications on the UTM-Neuroprocessor. For efficient VLSI implementation of the UTM-Neuroprocessor, the combined FPGA-VLSI approach was proposed. Correspondingly, the VLSI design of a 2x2 array computation engine, termed the Array_2x2 microchip, was developed in the AMI 0.5Âµm process technology and fabricated at the Europractice IC foundry. The fabricated Array_2x2 microchip can be applied to produce a 2x2 UTM-Neuroprocessor, in the combined FPGA-VLSI implementation approach. The design consumes an area of 16.9 mm2 on silicon and is encapsulated in 84-pin PGA package. SPICE simulations of the Array_2x2 design proved functionality at an operating frequency of 90 MHz. The microchip is able to deliver performances of up to 169.41 MCPS and 75.78 MCUPS MCUPS for a 2x2 UTM-Neuroprocessor 2005-12 Thesis http://eprints.utm.my/id/eprint/2946/ http://eprints.utm.my/id/eprint/2946/1/AvinashRajahMFKE2005.pdf application/pdf en public https://core.ac.uk/display/11779366 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Rajah, Avinash VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
description	As artificial neural networks continue to gain popularity in the domain of pattern recognition, there have been growing demands for these models to be executed at high-speeds. Thus, to cater to this need, the VLSI design and implementation of a neurohardware for high-speed pattern recognition is proposed in this research. The UTM-Neuroprocessor implements the Kohonen Neural Network for pattern classification. High-speed pattern classification by the neural paradigm is achieved through massively parallel execution based on the neuron-parallel processing approach. For proof of concept purposes, a 10x10 UTM-Neuroprocessor, which implements a 10x10 Kohonen network, was developed in this work. The design and rapid FPGA prototyping of the neuroprocessor was achieved using VHDL and the Altera Nios embedded system development kit. The FPGA-based prototype of the 10x10 UTM-Neuroprocessor is able to function at a frequency of 100 MHz and delivers performances up to 5.079 GCPS and 2.285 GCUPS. Software components, including a VB-based GUI, were also developed to allow execution of pattern recognition applications on the UTM-Neuroprocessor. For efficient VLSI implementation of the UTM-Neuroprocessor, the combined FPGA-VLSI approach was proposed. Correspondingly, the VLSI design of a 2x2 array computation engine, termed the Array_2x2 microchip, was developed in the AMI 0.5Âµm process technology and fabricated at the Europractice IC foundry. The fabricated Array_2x2 microchip can be applied to produce a 2x2 UTM-Neuroprocessor, in the combined FPGA-VLSI implementation approach. The design consumes an area of 16.9 mm2 on silicon and is encapsulated in 84-pin PGA package. SPICE simulations of the Array_2x2 design proved functionality at an operating frequency of 90 MHz. The microchip is able to deliver performances of up to 169.41 MCPS and 75.78 MCUPS MCUPS for a 2x2 UTM-Neuroprocessor
format	Thesis
qualification_level	Master's degree
author	Rajah, Avinash
author_facet	Rajah, Avinash
author_sort	Rajah, Avinash
title	VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
title_short	VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
title_full	VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
title_fullStr	VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
title_full_unstemmed	VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
title_sort	vlsi design of a neurohardware processor implementing the kohonen neural network algorithm
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2005
url	http://eprints.utm.my/id/eprint/2946/1/AvinashRajahMFKE2005.pdf
_version_	1747814430947672064

VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm

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