Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip

The push towards Systems-On-Chip (SoC) has triggered various research into the interconnect system. One such field that is garnering huge interest is on Network-On-Chip (NoC) interconnect. In an NoC, the performance depends heavily on the router. Improving the router’s performance will improve the o...

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Main Author:	Wang, Hsin We
Format:	Thesis
Published:	2011
Subjects:	TK Electrical engineering Electronics Nuclear engineering
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id	my-utm-ep.32057
record_format	uketd_dc
spelling	my-utm-ep.320572020-11-05T01:14:57Z Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip 2011-05 Wang, Hsin We TK Electrical engineering. Electronics Nuclear engineering The push towards Systems-On-Chip (SoC) has triggered various research into the interconnect system. One such field that is garnering huge interest is on Network-On-Chip (NoC) interconnect. In an NoC, the performance depends heavily on the router. Improving the router’s performance will improve the overall network performance. One way to improve the router’s performance is by adding virtual channels, which can reduce transfer latency. The main objective of this project is to develop a network router that uses wormhole routing with virtual channel support. The router is designed and implemented in synthesizeable Verilog HDL. Upon completion of conding, it is then verified functionally. Subsequently, the performance of the router is analyzed. The designed router will be deployed in a 4x4 mesh network, uses X-Y routing, has 3 virtual channel per input port with depth of four First-In-First-Out (FIFO) buffer. The entire design process starts with architecture definition and design. Once the required blocks and functionalities such as virtual channel controller, arbiter, buffers and crossbars are defined, they are then coded and integrated. Verification is done from bottoms up starting from individual units. Simulation results show that virtual channel would improve network performance in high traffic load condition, where the latency is improved by between 36% to 62%. Performance is slighly degraded, by about 4.3%, under light traffic conditions due to more complex arbitration. In terms of resource utilization, the addition of 3 virtual channels with FIFO depth of 4 will increase the total number of logic elements by 136%, registers by 131% and memory elements by 200%. 2011-05 Thesis http://eprints.utm.my/id/eprint/32057/ masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Wang, Hsin We Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip
description	The push towards Systems-On-Chip (SoC) has triggered various research into the interconnect system. One such field that is garnering huge interest is on Network-On-Chip (NoC) interconnect. In an NoC, the performance depends heavily on the router. Improving the router’s performance will improve the overall network performance. One way to improve the router’s performance is by adding virtual channels, which can reduce transfer latency. The main objective of this project is to develop a network router that uses wormhole routing with virtual channel support. The router is designed and implemented in synthesizeable Verilog HDL. Upon completion of conding, it is then verified functionally. Subsequently, the performance of the router is analyzed. The designed router will be deployed in a 4x4 mesh network, uses X-Y routing, has 3 virtual channel per input port with depth of four First-In-First-Out (FIFO) buffer. The entire design process starts with architecture definition and design. Once the required blocks and functionalities such as virtual channel controller, arbiter, buffers and crossbars are defined, they are then coded and integrated. Verification is done from bottoms up starting from individual units. Simulation results show that virtual channel would improve network performance in high traffic load condition, where the latency is improved by between 36% to 62%. Performance is slighly degraded, by about 4.3%, under light traffic conditions due to more complex arbitration. In terms of resource utilization, the addition of 3 virtual channels with FIFO depth of 4 will increase the total number of logic elements by 136%, registers by 131% and memory elements by 200%.
format	Thesis
qualification_level	Master's degree
author	Wang, Hsin We
author_facet	Wang, Hsin We
author_sort	Wang, Hsin We
title	Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip
title_short	Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip
title_full	Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip
title_fullStr	Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip
title_full_unstemmed	Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip
title_sort	enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2011
_version_	1747815910922518528

Enhanced wormhole router and network adapter architectures with virtual circuit support for network on chip

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