Study on FPGA based IIR filter using quantitative approach

The main goal of this project is to design a digital filter which is compatible between simulation tool (software) and hardware implementation using Matlab and Quartuss II. The filter is realized in Direct Form II biquad architecture to achieve scalable and expandable design which can be cascaded if...

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Main Author:	Ow, Shin Tsyr
Format:	Thesis
Language:	English
Published:	2012
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/32541/5/OwShenWahMFKE2012.pdf
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id	my-utm-ep.32541
record_format	uketd_dc
spelling	my-utm-ep.325412018-04-27T01:22:01Z Study on FPGA based IIR filter using quantitative approach 2012-06 Ow, Shin Tsyr TK Electrical engineering. Electronics Nuclear engineering The main goal of this project is to design a digital filter which is compatible between simulation tool (software) and hardware implementation using Matlab and Quartuss II. The filter is realized in Direct Form II biquad architecture to achieve scalable and expandable design which can be cascaded if necessary. Filter quantization procedure is presented based on the finite word-length arithmetic to determine the bit length of the filter’s digital parameters as accurate as possible. With the resulting bit-true model, hardware design implementation using Verilog RTL for Altera FPGA is then performed. A biquad filter in FPGA, using numerous hardware realization methods, namely fully combinational, combinational-sequential and bit serial are designed and performance analysis is carried out by comparing their efficiency and area. The design is then optimized further to be more cost-effective by implementing the bit-serial arithmetic architecture where multipliers are replaced with lookup table (LUT). According to the simulation result, fully-combinational is the fastest and the most expensive approach with unconstrained resource utilization while combinational-sequential compromises between area and speed with limited resources. On the other hand, bit-serial model achieves highest maximum frequency with lowest propagation delay between registers. Optimization with LUT usage is a hybrid model of fully-combinational and bit-serial which it balances up the pros and cons by improving the maximum frequency of fully combinational and reducing the total execution time of bit-serial approach. 2012-06 Thesis http://eprints.utm.my/id/eprint/32541/ http://eprints.utm.my/id/eprint/32541/5/OwShenWahMFKE2012.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Ow, Shin Tsyr Study on FPGA based IIR filter using quantitative approach
description	The main goal of this project is to design a digital filter which is compatible between simulation tool (software) and hardware implementation using Matlab and Quartuss II. The filter is realized in Direct Form II biquad architecture to achieve scalable and expandable design which can be cascaded if necessary. Filter quantization procedure is presented based on the finite word-length arithmetic to determine the bit length of the filter’s digital parameters as accurate as possible. With the resulting bit-true model, hardware design implementation using Verilog RTL for Altera FPGA is then performed. A biquad filter in FPGA, using numerous hardware realization methods, namely fully combinational, combinational-sequential and bit serial are designed and performance analysis is carried out by comparing their efficiency and area. The design is then optimized further to be more cost-effective by implementing the bit-serial arithmetic architecture where multipliers are replaced with lookup table (LUT). According to the simulation result, fully-combinational is the fastest and the most expensive approach with unconstrained resource utilization while combinational-sequential compromises between area and speed with limited resources. On the other hand, bit-serial model achieves highest maximum frequency with lowest propagation delay between registers. Optimization with LUT usage is a hybrid model of fully-combinational and bit-serial which it balances up the pros and cons by improving the maximum frequency of fully combinational and reducing the total execution time of bit-serial approach.
format	Thesis
qualification_level	Master's degree
author	Ow, Shin Tsyr
author_facet	Ow, Shin Tsyr
author_sort	Ow, Shin Tsyr
title	Study on FPGA based IIR filter using quantitative approach
title_short	Study on FPGA based IIR filter using quantitative approach
title_full	Study on FPGA based IIR filter using quantitative approach
title_fullStr	Study on FPGA based IIR filter using quantitative approach
title_full_unstemmed	Study on FPGA based IIR filter using quantitative approach
title_sort	study on fpga based iir filter using quantitative approach
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2012
url	http://eprints.utm.my/id/eprint/32541/5/OwShenWahMFKE2012.pdf
_version_	1747816027205402624

Study on FPGA based IIR filter using quantitative approach

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