System verilog RTL modeling with embedded assertions

This project has a final goal of developing a new methodology of pre-silicon and post-silicon validation which helps in better IP delivery to SOC system. Hardware Description Language, System Verilog is adopted in doing RTL modeling and System Verilog Assertions are used in verifications. Both desig...

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Main Author:	Chow, Chee Siang
Format:	Thesis
Language:	English
Published:	2012
Subjects:	T Technology (General)
Online Access:	http://eprints.utm.my/id/eprint/32554/1/ChowCheeSiangMFKE2012.pdf
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id	my-utm-ep.32554
record_format	uketd_dc
spelling	my-utm-ep.325542017-08-22T00:56:59Z System verilog RTL modeling with embedded assertions 2012 Chow, Chee Siang T Technology (General) This project has a final goal of developing a new methodology of pre-silicon and post-silicon validation which helps in better IP delivery to SOC system. Hardware Description Language, System Verilog is adopted in doing RTL modeling and System Verilog Assertions are used in verifications. Both design and validation components are combined into single module with pre-defined compiler directive. The conversion of non-synthesizable System Verilog assertions into synthesizable format enables designers to integrate some built in checkers into own design for pre-silicon and post silicon validation. By having synthesizable assertions in the design, the validation cycle can be shorten because some of the testing can be carried out using FPGA. The testing on FPGA can run much faster than simulation which has dependency on simulator tool. Every System Verilog assertion is being modeled as a real hardware component and embedded into design block. The project provides the methodology and examples of how to synthesize System Verilog Assertions using component cascading method to represent temporal expressions used in non-synthesizable assertions. 2012 Thesis http://eprints.utm.my/id/eprint/32554/ http://eprints.utm.my/id/eprint/32554/1/ChowCheeSiangMFKE2012.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:77432?queryType=vitalDismax&query=System+verilog+RTL+modeling+with+embedded+assertions&public=true masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	T Technology (General)
spellingShingle	T Technology (General) Chow, Chee Siang System verilog RTL modeling with embedded assertions
description	This project has a final goal of developing a new methodology of pre-silicon and post-silicon validation which helps in better IP delivery to SOC system. Hardware Description Language, System Verilog is adopted in doing RTL modeling and System Verilog Assertions are used in verifications. Both design and validation components are combined into single module with pre-defined compiler directive. The conversion of non-synthesizable System Verilog assertions into synthesizable format enables designers to integrate some built in checkers into own design for pre-silicon and post silicon validation. By having synthesizable assertions in the design, the validation cycle can be shorten because some of the testing can be carried out using FPGA. The testing on FPGA can run much faster than simulation which has dependency on simulator tool. Every System Verilog assertion is being modeled as a real hardware component and embedded into design block. The project provides the methodology and examples of how to synthesize System Verilog Assertions using component cascading method to represent temporal expressions used in non-synthesizable assertions.
format	Thesis
qualification_level	Master's degree
author	Chow, Chee Siang
author_facet	Chow, Chee Siang
author_sort	Chow, Chee Siang
title	System verilog RTL modeling with embedded assertions
title_short	System verilog RTL modeling with embedded assertions
title_full	System verilog RTL modeling with embedded assertions
title_fullStr	System verilog RTL modeling with embedded assertions
title_full_unstemmed	System verilog RTL modeling with embedded assertions
title_sort	system verilog rtl modeling with embedded assertions
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2012
url	http://eprints.utm.my/id/eprint/32554/1/ChowCheeSiangMFKE2012.pdf
_version_	1747816030399365120

System verilog RTL modeling with embedded assertions

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