Functional test generation using micro operation fault model

As semiconductor technology advances further into nanometer regime, integrated circuit testing and validation continues to play a very important role to ensure high quality product. Conventionally, test patterns are generated from a gate level netlist using test generation tool. However, as the digi...

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Main Author:	Ong, Hui Yien
Format:	Thesis
Language:	English
Published:	2011
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/33347/1/OngHuiYienMFKE2011.pdf
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id	my-utm-ep.33347
record_format	uketd_dc
spelling	my-utm-ep.333472021-05-23T10:32:53Z Functional test generation using micro operation fault model 2011 Ong, Hui Yien TK Electrical engineering. Electronics Nuclear engineering As semiconductor technology advances further into nanometer regime, integrated circuit testing and validation continues to play a very important role to ensure high quality product. Conventionally, test patterns are generated from a gate level netlist using test generation tool. However, as the digital design increases in complexity, the gate level test generation process becomes more complicated and time consuming. As an extended alternative to this, functional fault model like micro operation fault model was introduced. However, in order to implement this, proper automation is necessary while minimizing intensive manual labor. Unfortunately, currently there is only proprietary version of automation available. In this project, an automated platform to generate test pattern using micro operation fault model was built using Perl programming language. The methodology involves conversion of behavioral model of design under test into extended finite state machine. This is followed by micro operation fault detection, fault activation and fault propagation with all the corresponding constraint sequences captured and converted into constraint model using SystemVerilog, a hardware description language. These models of fault free and intended faulty circuit were fed into a constraint solver tool, VCS by Synopsys to generate the test pattern. For verification purpose, these test patterns were validated by simulating the circuit using Altera Quartus II tool. The result of this project shows that reasonable fault coverage was achieved using this methodology. 2011 Thesis http://eprints.utm.my/id/eprint/33347/ http://eprints.utm.my/id/eprint/33347/1/OngHuiYienMFKE2011.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:69846?queryType=vitalDismax&query=Functional+test+generation+using+micro+operation+fault+model&public=true masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Ong, Hui Yien Functional test generation using micro operation fault model
description	As semiconductor technology advances further into nanometer regime, integrated circuit testing and validation continues to play a very important role to ensure high quality product. Conventionally, test patterns are generated from a gate level netlist using test generation tool. However, as the digital design increases in complexity, the gate level test generation process becomes more complicated and time consuming. As an extended alternative to this, functional fault model like micro operation fault model was introduced. However, in order to implement this, proper automation is necessary while minimizing intensive manual labor. Unfortunately, currently there is only proprietary version of automation available. In this project, an automated platform to generate test pattern using micro operation fault model was built using Perl programming language. The methodology involves conversion of behavioral model of design under test into extended finite state machine. This is followed by micro operation fault detection, fault activation and fault propagation with all the corresponding constraint sequences captured and converted into constraint model using SystemVerilog, a hardware description language. These models of fault free and intended faulty circuit were fed into a constraint solver tool, VCS by Synopsys to generate the test pattern. For verification purpose, these test patterns were validated by simulating the circuit using Altera Quartus II tool. The result of this project shows that reasonable fault coverage was achieved using this methodology.
format	Thesis
qualification_level	Master's degree
author	Ong, Hui Yien
author_facet	Ong, Hui Yien
author_sort	Ong, Hui Yien
title	Functional test generation using micro operation fault model
title_short	Functional test generation using micro operation fault model
title_full	Functional test generation using micro operation fault model
title_fullStr	Functional test generation using micro operation fault model
title_full_unstemmed	Functional test generation using micro operation fault model
title_sort	functional test generation using micro operation fault model
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2011
url	http://eprints.utm.my/id/eprint/33347/1/OngHuiYienMFKE2011.pdf
_version_	1747816139360043008

Functional test generation using micro operation fault model

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