Functional test generation using micro operation fault model
As semiconductor technology advances further into nanometer regime, integrated circuit testing and validation continues to play a very important role to ensure high quality product. Conventionally, test patterns are generated from a gate level netlist using test generation tool. However, as the digi...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2011
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/33347/1/OngHuiYienMFKE2011.pdf |
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