High-performance digital filter in FPGA

Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application- specific integrated circuits (ASICs) for higher rates. Based on the study digital filter which is Infin...

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Main Author:	Mohd. Yusof, Siti Suhaila
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/39047/5/SitiSuhailaMohdYusofMFKE2013.pdf
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spelling	my-utm-ep.390472017-07-17T05:07:27Z High-performance digital filter in FPGA 2013-06 Mohd. Yusof, Siti Suhaila TK Electrical engineering. Electronics Nuclear engineering Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application- specific integrated circuits (ASICs) for higher rates. Based on the study digital filter which is Infinite Impulse Response (IIR) filter, the filter is generally used in the lower sample rates, that is less than 200 kHz (2009) [2]. These filters are used over a wide range of sample rates and are well supported in terms of tools, software, and IP cores. In this research, a high performance and area optimized infinite impulse response (IIR) filter realization in field programmable gate arrays (FPGAs) is proposed. The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. The main goal of this project is to mapping data flow graphs (DFGs) from the BiQuad architecture direct form II of Infinite Impulse Response filtering algorithms into application specific structure is considered. This filter realizes BiQuad Methods was structured with the high throughput, high clock frequency (Fmax), low Critical Path Delay (CPD), and low Latency (L). Optimization method is proposed which provides designing pipelined structures, concurrent, minimal resource utilization and minimized sensitivity to truncation errors. A digital filter which is compatible with simulation tool (software) Verilog HDL Quartus II and Matlab presented in preliminary results chapter 5. 2013-06 Thesis http://eprints.utm.my/id/eprint/39047/ http://eprints.utm.my/id/eprint/39047/5/SitiSuhailaMohdYusofMFKE2013.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Mohd. Yusof, Siti Suhaila High-performance digital filter in FPGA
description	Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application- specific integrated circuits (ASICs) for higher rates. Based on the study digital filter which is Infinite Impulse Response (IIR) filter, the filter is generally used in the lower sample rates, that is less than 200 kHz (2009) [2]. These filters are used over a wide range of sample rates and are well supported in terms of tools, software, and IP cores. In this research, a high performance and area optimized infinite impulse response (IIR) filter realization in field programmable gate arrays (FPGAs) is proposed. The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. The main goal of this project is to mapping data flow graphs (DFGs) from the BiQuad architecture direct form II of Infinite Impulse Response filtering algorithms into application specific structure is considered. This filter realizes BiQuad Methods was structured with the high throughput, high clock frequency (Fmax), low Critical Path Delay (CPD), and low Latency (L). Optimization method is proposed which provides designing pipelined structures, concurrent, minimal resource utilization and minimized sensitivity to truncation errors. A digital filter which is compatible with simulation tool (software) Verilog HDL Quartus II and Matlab presented in preliminary results chapter 5.
format	Thesis
qualification_level	Master's degree
author	Mohd. Yusof, Siti Suhaila
author_facet	Mohd. Yusof, Siti Suhaila
author_sort	Mohd. Yusof, Siti Suhaila
title	High-performance digital filter in FPGA
title_short	High-performance digital filter in FPGA
title_full	High-performance digital filter in FPGA
title_fullStr	High-performance digital filter in FPGA
title_full_unstemmed	High-performance digital filter in FPGA
title_sort	high-performance digital filter in fpga
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2013
url	http://eprints.utm.my/id/eprint/39047/5/SitiSuhailaMohdYusofMFKE2013.pdf
_version_	1747816541689217024

High-performance digital filter in FPGA

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