A high speed 2D convolution hardware module for image processing applications in hardware

Visual information plays an essential role in almost all areas of our life, hence making image processing a very important subject of research. Image processing can be divided into digital image processing and analog image processing. Various applications including video surveillance, target recogni...

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Main Author:	Baba, Beenal
Format:	Thesis
Language:	English
Published:	2013
Subjects:	QA75 Electronic computers Computer science
Online Access:	http://eprints.utm.my/id/eprint/39159/6/BeenalBabaMFKE2013.pdf
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id	my-utm-ep.39159
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spelling	my-utm-ep.391592017-07-11T04:09:09Z A high speed 2D convolution hardware module for image processing applications in hardware 2013-06 Baba, Beenal QA75 Electronic computers. Computer science Visual information plays an essential role in almost all areas of our life, hence making image processing a very important subject of research. Image processing can be divided into digital image processing and analog image processing. Various applications including video surveillance, target recognition, and image enhancement requires digital image processing. In such applications, for functions like image filtering, image restoration, object tracking, template matching and many others, the spatial domain two-dimensional (2D) convolution plays a pivotal role. These functions are usually implemented in software previously but are slowly moving towards hardware for speed, as hardware allows pipelining and parallelism. The main objective of this project is to develop an image processing algorithm, 2D convolution. This project starts with architecture definition, followed by design implementation, verification and burning the design on FPGA. At the architecture definition stage, two different datapaths architectures are explored, Barrel Shifter and Multiplier. Basic design specifications are set and then design implementation is pursued. Verilog HDL is used to code the design; Quartus II tool is used for compilation and synthesis. The functionality and timing of the design is then verified using Modelsim tool before bringing the design to FPGA and tested using Quartus II’s SignalTapII Logic Analyzer. Additionly, the design is further verified with real image pixels and compared the output pixels with that obtained from software (MATLAB). Altera Quartus II compilation report shows the 2D convolution design with Barrel Shifter can run at higher frequency compared to multiplier, and the design with off chip RAM runs faster than the design with on chip RAM. 2013-06 Thesis http://eprints.utm.my/id/eprint/39159/ http://eprints.utm.my/id/eprint/39159/6/BeenalBabaMFKE2013.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Biosciences and Medical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	QA75 Electronic computers Computer science
spellingShingle	QA75 Electronic computers Computer science Baba, Beenal A high speed 2D convolution hardware module for image processing applications in hardware
description	Visual information plays an essential role in almost all areas of our life, hence making image processing a very important subject of research. Image processing can be divided into digital image processing and analog image processing. Various applications including video surveillance, target recognition, and image enhancement requires digital image processing. In such applications, for functions like image filtering, image restoration, object tracking, template matching and many others, the spatial domain two-dimensional (2D) convolution plays a pivotal role. These functions are usually implemented in software previously but are slowly moving towards hardware for speed, as hardware allows pipelining and parallelism. The main objective of this project is to develop an image processing algorithm, 2D convolution. This project starts with architecture definition, followed by design implementation, verification and burning the design on FPGA. At the architecture definition stage, two different datapaths architectures are explored, Barrel Shifter and Multiplier. Basic design specifications are set and then design implementation is pursued. Verilog HDL is used to code the design; Quartus II tool is used for compilation and synthesis. The functionality and timing of the design is then verified using Modelsim tool before bringing the design to FPGA and tested using Quartus II’s SignalTapII Logic Analyzer. Additionly, the design is further verified with real image pixels and compared the output pixels with that obtained from software (MATLAB). Altera Quartus II compilation report shows the 2D convolution design with Barrel Shifter can run at higher frequency compared to multiplier, and the design with off chip RAM runs faster than the design with on chip RAM.
format	Thesis
qualification_level	Master's degree
author	Baba, Beenal
author_facet	Baba, Beenal
author_sort	Baba, Beenal
title	A high speed 2D convolution hardware module for image processing applications in hardware
title_short	A high speed 2D convolution hardware module for image processing applications in hardware
title_full	A high speed 2D convolution hardware module for image processing applications in hardware
title_fullStr	A high speed 2D convolution hardware module for image processing applications in hardware
title_full_unstemmed	A high speed 2D convolution hardware module for image processing applications in hardware
title_sort	high speed 2d convolution hardware module for image processing applications in hardware
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Biosciences and Medical Engineering
publishDate	2013
url	http://eprints.utm.my/id/eprint/39159/6/BeenalBabaMFKE2013.pdf
_version_	1747816542670684160

A high speed 2D convolution hardware module for image processing applications in hardware

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