Object-oriented test pattern generator and logic simulator for combinational circuits

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主要作者: Ooi, Chia Yee
格式: Thesis
出版: 2003
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id my-utm-ep.42691
record_format uketd_dc
spelling my-utm-ep.426912017-10-06T08:21:16Z Object-oriented test pattern generator and logic simulator for combinational circuits 2003 Ooi, Chia Yee TK Electrical engineering. Electronics Nuclear engineering 2003 Thesis http://eprints.utm.my/id/eprint/42691/ http://libraryopac.utm.my/client/en_AU/main/search/results?qu=Object-oriented+test+pattern+generator+and+logic+simulator+for+combinational+circuits&te= masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution Universiti Teknologi Malaysia
collection UTM Institutional Repository
topic TK Electrical engineering
Electronics Nuclear engineering
spellingShingle TK Electrical engineering
Electronics Nuclear engineering
Ooi, Chia Yee
Object-oriented test pattern generator and logic simulator for combinational circuits
description
format Thesis
qualification_level Master's degree
author Ooi, Chia Yee
author_facet Ooi, Chia Yee
author_sort Ooi, Chia Yee
title Object-oriented test pattern generator and logic simulator for combinational circuits
title_short Object-oriented test pattern generator and logic simulator for combinational circuits
title_full Object-oriented test pattern generator and logic simulator for combinational circuits
title_fullStr Object-oriented test pattern generator and logic simulator for combinational circuits
title_full_unstemmed Object-oriented test pattern generator and logic simulator for combinational circuits
title_sort object-oriented test pattern generator and logic simulator for combinational circuits
granting_institution Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department Faculty of Electrical Engineering
publishDate 2003
_version_ 1747816831201050624