VHDL modelling and asic design of a shortest-path processor core for network routing

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Main Author: Teoh, Giap Seng
Format: Thesis
Published: 2003
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id my-utm-ep.42788
record_format uketd_dc
spelling my-utm-ep.427882017-08-30T02:18:41Z VHDL modelling and asic design of a shortest-path processor core for network routing 2003 Teoh, Giap Seng TK Electrical engineering. Electronics Nuclear engineering 2003 Thesis http://eprints.utm.my/id/eprint/42788/ http://libraryopac.utm.my/client/en_AU/main/search/detailnonmodal/ent:$002f$002fSD_ILS$002f0$002fSD_ILS:360530/one?qu=VHDL+modelling+and+asic+design+of+a+shortest-path+processor+core+for+network+routing masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution Universiti Teknologi Malaysia
collection UTM Institutional Repository
topic TK Electrical engineering
Electronics Nuclear engineering
spellingShingle TK Electrical engineering
Electronics Nuclear engineering
Teoh, Giap Seng
VHDL modelling and asic design of a shortest-path processor core for network routing
description
format Thesis
qualification_level Master's degree
author Teoh, Giap Seng
author_facet Teoh, Giap Seng
author_sort Teoh, Giap Seng
title VHDL modelling and asic design of a shortest-path processor core for network routing
title_short VHDL modelling and asic design of a shortest-path processor core for network routing
title_full VHDL modelling and asic design of a shortest-path processor core for network routing
title_fullStr VHDL modelling and asic design of a shortest-path processor core for network routing
title_full_unstemmed VHDL modelling and asic design of a shortest-path processor core for network routing
title_sort vhdl modelling and asic design of a shortest-path processor core for network routing
granting_institution Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department Faculty of Electrical Engineering
publishDate 2003
_version_ 1747816854874750976