Arbitration schemes of wishbone on chip bus system

In the SoC development, the compatibility of IP cores is one of the challenges that need to be addressed carefully. Most of the time, IP cores is having different input output specifications with new platform. The Wishbone SoC interconnection Architecture is aim to provide a good solution for SoC in...

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Main Author:	Ong, Kok Tong
Format:	Thesis
Language:	English
Published:	2014
Subjects:	TK7885-7895 Computer engineer Computer hardware
Online Access:	http://eprints.utm.my/id/eprint/47999/25/OngKokTongMFKE2014.pdf
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id	my-utm-ep.47999
record_format	uketd_dc
spelling	my-utm-ep.479992017-08-09T05:40:23Z Arbitration schemes of wishbone on chip bus system 2014-06 Ong, Kok Tong TK7885-7895 Computer engineer. Computer hardware In the SoC development, the compatibility of IP cores is one of the challenges that need to be addressed carefully. Most of the time, IP cores is having different input output specifications with new platform. The Wishbone SoC interconnection Architecture is aim to provide a good solution for SoC integration issues by having common interface specifications. In this project, the Wishbone on-chip computer bus for 32-bit cores is implemented in system verilog along with three different arbitration schemes which are fixed priority, round robin, and priority control. On top of that, the optimum transfer size for Wishbone bus in terms of bus throughput and average wait cycle is presented as well. It is found that the optimum transfer size for Wishbone bus is 64 bytes. Finally, the Wishbone bus is used to examine the bus performance of different arbitration schemes in Modelsim simulation. Round robin arbitration scheme is the best among three arbitration schemes in terms of bus throughput, logic complexity, and maximum wait cycle. 2014-06 Thesis http://eprints.utm.my/id/eprint/47999/ http://eprints.utm.my/id/eprint/47999/25/OngKokTongMFKE2014.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK7885-7895 Computer engineer Computer hardware
spellingShingle	TK7885-7895 Computer engineer Computer hardware Ong, Kok Tong Arbitration schemes of wishbone on chip bus system
description	In the SoC development, the compatibility of IP cores is one of the challenges that need to be addressed carefully. Most of the time, IP cores is having different input output specifications with new platform. The Wishbone SoC interconnection Architecture is aim to provide a good solution for SoC integration issues by having common interface specifications. In this project, the Wishbone on-chip computer bus for 32-bit cores is implemented in system verilog along with three different arbitration schemes which are fixed priority, round robin, and priority control. On top of that, the optimum transfer size for Wishbone bus in terms of bus throughput and average wait cycle is presented as well. It is found that the optimum transfer size for Wishbone bus is 64 bytes. Finally, the Wishbone bus is used to examine the bus performance of different arbitration schemes in Modelsim simulation. Round robin arbitration scheme is the best among three arbitration schemes in terms of bus throughput, logic complexity, and maximum wait cycle.
format	Thesis
qualification_level	Master's degree
author	Ong, Kok Tong
author_facet	Ong, Kok Tong
author_sort	Ong, Kok Tong
title	Arbitration schemes of wishbone on chip bus system
title_short	Arbitration schemes of wishbone on chip bus system
title_full	Arbitration schemes of wishbone on chip bus system
title_fullStr	Arbitration schemes of wishbone on chip bus system
title_full_unstemmed	Arbitration schemes of wishbone on chip bus system
title_sort	arbitration schemes of wishbone on chip bus system
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2014
url	http://eprints.utm.my/id/eprint/47999/25/OngKokTongMFKE2014.pdf
_version_	1747817283148840960

Arbitration schemes of wishbone on chip bus system

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