Advanced encryption standard (AES) coprocessor

The purpose of this project is to design a high throughput Advanced Encryption Standard (AES) coprocessor using SystemVerilog Hardware Description Language (HDL). AES coprocessor has been widely used to offload the compute intensive cryptography tasks from the main processor due to its efficiency an...

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Main Author:	Lim, Joo Song
Format:	Thesis
Language:	English
Published:	2014
Subjects:	TK7885-7895 Computer engineer Computer hardware
Online Access:	http://eprints.utm.my/id/eprint/48711/25/LimJooSongMFKE2014.pdf
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id	my-utm-ep.48711
record_format	uketd_dc
spelling	my-utm-ep.487112020-06-18T00:57:58Z Advanced encryption standard (AES) coprocessor 2014-06 Lim, Joo Song TK7885-7895 Computer engineer. Computer hardware The purpose of this project is to design a high throughput Advanced Encryption Standard (AES) coprocessor using SystemVerilog Hardware Description Language (HDL). AES coprocessor has been widely used to offload the compute intensive cryptography tasks from the main processor due to its efficiency and performance compare to the pure software solution. Conventional AES core design using iterative loop approach is not optimized for high throughput operation. Therefore pipelined architecture is the most recommend method for high throughput design. However most of the high throughput designs tend to reliance on vendor specific features to boost the performance. This has caused the design becomes non-generic and low portability. A bottom-up approach has being used to design the coprocessor. A non-pipelined AES coprocessor was being built first as the baseline design. Then different types of pipelined implementation were being explored for possible adoption. The throughput, size and potential enhancement are the main criteria being evaluated. It was discovered that the Full Outer-Round pipelined architecture is the most efficient design in term of throughput and size. From the analysis of the Full Outer-Round pipelined model, a novel method called Single Datapath Dual Output (SDDO) has been proposed to double the throughput of the pipelined coprocessor. Simulation results demonstrated that SDDO architecture is able to double the throughput of the pipelined design while only requires 7% of additional resource to implement. 2014-06 Thesis http://eprints.utm.my/id/eprint/48711/ http://eprints.utm.my/id/eprint/48711/25/LimJooSongMFKE2014.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:86177 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK7885-7895 Computer engineer Computer hardware
spellingShingle	TK7885-7895 Computer engineer Computer hardware Lim, Joo Song Advanced encryption standard (AES) coprocessor
description	The purpose of this project is to design a high throughput Advanced Encryption Standard (AES) coprocessor using SystemVerilog Hardware Description Language (HDL). AES coprocessor has been widely used to offload the compute intensive cryptography tasks from the main processor due to its efficiency and performance compare to the pure software solution. Conventional AES core design using iterative loop approach is not optimized for high throughput operation. Therefore pipelined architecture is the most recommend method for high throughput design. However most of the high throughput designs tend to reliance on vendor specific features to boost the performance. This has caused the design becomes non-generic and low portability. A bottom-up approach has being used to design the coprocessor. A non-pipelined AES coprocessor was being built first as the baseline design. Then different types of pipelined implementation were being explored for possible adoption. The throughput, size and potential enhancement are the main criteria being evaluated. It was discovered that the Full Outer-Round pipelined architecture is the most efficient design in term of throughput and size. From the analysis of the Full Outer-Round pipelined model, a novel method called Single Datapath Dual Output (SDDO) has been proposed to double the throughput of the pipelined coprocessor. Simulation results demonstrated that SDDO architecture is able to double the throughput of the pipelined design while only requires 7% of additional resource to implement.
format	Thesis
qualification_level	Master's degree
author	Lim, Joo Song
author_facet	Lim, Joo Song
author_sort	Lim, Joo Song
title	Advanced encryption standard (AES) coprocessor
title_short	Advanced encryption standard (AES) coprocessor
title_full	Advanced encryption standard (AES) coprocessor
title_fullStr	Advanced encryption standard (AES) coprocessor
title_full_unstemmed	Advanced encryption standard (AES) coprocessor
title_sort	advanced encryption standard (aes) coprocessor
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2014
url	http://eprints.utm.my/id/eprint/48711/25/LimJooSongMFKE2014.pdf
_version_	1747817457117036544

Advanced encryption standard (AES) coprocessor

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