CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE

This project report focuses on the multiple-value logic (MVL) or commonly known as ternary logic gates by using carbon nanotube (CNT) FETs devices (CNTFETs). It is shown ternary logic has promising future in CNTFETs when compare to conventional binary logic design, due to its simplicity and energy e...

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Main Author:	Ee, Poey Guan
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/48894/25/EePoeyGuanMFKE2015.pdf
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spelling	my-utm-ep.488942020-07-05T06:52:24Z CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE 2015-01 Ee, Poey Guan TK Electrical engineering. Electronics Nuclear engineering This project report focuses on the multiple-value logic (MVL) or commonly known as ternary logic gates by using carbon nanotube (CNT) FETs devices (CNTFETs). It is shown ternary logic has promising future in CNTFETs when compare to conventional binary logic design, due to its simplicity and energy efficiency in digital design reduced circuit overhead such as chip area and interconnection. In this research, existing CNTFET-based binary inverter and standard ternary inverter with resistive-load (STI-R) for comparison with the other three types of inverter are proposed - Complementary Standard Ternary Inverter (CSTI); Standard Ternary Inverter with 1 resistor and 3 NCNTFET (NSTI-R); Standard Ternary Inverter with 1 resistor and 3 PCNTFET (PSTI-R) to analysis the performance, structure design and application. In addition, the research covers all the basic logic Ternary NAND gate and Ternary NOR gate for further benchmarking. All simulation results using SPICE are obtained and analyzed in the Direct Current (DC) setting and verifed using half adder. Further study behavior of ternary logic includes the implementation of partial binary design into the ternary design and performance benchmarking. The result shows the CSTI have advantage on low power design with low leakage while NSTI-R has advantage on high-speed design inverter. In addition, partial binary design in the arithmetic circuit ternary design with CSTI shows added advantage in a low power design. 2015-01 Thesis http://eprints.utm.my/id/eprint/48894/ http://eprints.utm.my/id/eprint/48894/25/EePoeyGuanMFKE2015.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:86729 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Ee, Poey Guan CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
description	This project report focuses on the multiple-value logic (MVL) or commonly known as ternary logic gates by using carbon nanotube (CNT) FETs devices (CNTFETs). It is shown ternary logic has promising future in CNTFETs when compare to conventional binary logic design, due to its simplicity and energy efficiency in digital design reduced circuit overhead such as chip area and interconnection. In this research, existing CNTFET-based binary inverter and standard ternary inverter with resistive-load (STI-R) for comparison with the other three types of inverter are proposed - Complementary Standard Ternary Inverter (CSTI); Standard Ternary Inverter with 1 resistor and 3 NCNTFET (NSTI-R); Standard Ternary Inverter with 1 resistor and 3 PCNTFET (PSTI-R) to analysis the performance, structure design and application. In addition, the research covers all the basic logic Ternary NAND gate and Ternary NOR gate for further benchmarking. All simulation results using SPICE are obtained and analyzed in the Direct Current (DC) setting and verifed using half adder. Further study behavior of ternary logic includes the implementation of partial binary design into the ternary design and performance benchmarking. The result shows the CSTI have advantage on low power design with low leakage while NSTI-R has advantage on high-speed design inverter. In addition, partial binary design in the arithmetic circuit ternary design with CSTI shows added advantage in a low power design.
format	Thesis
qualification_level	Master's degree
author	Ee, Poey Guan
author_facet	Ee, Poey Guan
author_sort	Ee, Poey Guan
title	CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
title_short	CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
title_full	CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
title_fullStr	CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
title_full_unstemmed	CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
title_sort	cnfet-based design ternary logic design and arithmetic circuit simulation using hspice
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2015
url	http://eprints.utm.my/id/eprint/48894/25/EePoeyGuanMFKE2015.pdf
_version_	1747817497718947840

CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE

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