A hardware implementation of Rivest-Shamir-Adleman co-processor for resource constrained embedded systems
The concern with security problems has been rapidly increasing as computers and Internet services become a more pervasive part of our daily life. This need is further fueled by the advent of mobile electronic devices like smart cards, mobile phones and hardware tokens. Public key cryptographic syste...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2006
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/5286/1/ArulPaniandiMFKE2006.pdf |
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| Summary: | The concern with security problems has been rapidly increasing as computers and Internet services become a more pervasive part of our daily life. This need is further fueled by the advent of mobile electronic devices like smart cards, mobile phones and hardware tokens. Public key cryptographic systems such as RSA (Rivest- Shamir-Adleman) are vital in providing this security in terms of authentication, private key exchange, and digital signatures. Unfortunately, current RSA implementations are either resource exhaustive or too slow. In this thesis, a fast and configurable hardware implementation of the RSA algorithm for public key cryptography is presented that addresses the issues above. The designed RSA coprocessor core is actually a modular exponentiation hardware engine, which is the basic arithmetic operation in implementing a RSA public key encryption and decryption algorithm. The computation intensive modular multiplication operation is based on the Montgomery’s algorithm and implemented using systolic array architecture. The modules in the RSA co-processor are modeled using VHDL hardware description language before being integrated with Altera’s softcore general-purpose processor, Nios II, and standard peripherals to form a complete cryptosystem in SoPC environment. Embedded C language codes are then written to test the functionality of the RSA co-processor on hardware. Upon verification, a demonstration application prototype that performs RSA encryption and decryption is developed using Visual Basic 6.0. This RSA co-processor core is able to encrypt and decrypt data with variable key lengths up to 4096 bits. The 1024 bit implementation uses 7000 Logic Elements (LE) on the Altera Stratix EP1S40-F780C5 FPGA development board which roughly translates to 49,000 gates. Encryption takes 2 ms while decryption takes 79 ms with the clock frequency of 40MHz. The speed and area constraint achieved is comparable and even better than several other research and commercial implementations. |
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