Modeling the effects of phonon scattering in carbon nanotube and silicon nanowire field-effect transistors
Carbon nanotubes (CNT) and silicon nanowires (Si NW) are nominated as the channel material for the next generation of transistors. Although previous works have shown that both CNT- and Si NW- based Field-Effect-Transistors (FET) are able to deliver better performance than conventional devices, phono...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/54069/1/ChinHueiChaengMFKE2015.pdf |
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| Summary: | Carbon nanotubes (CNT) and silicon nanowires (Si NW) are nominated as the channel material for the next generation of transistors. Although previous works have shown that both CNT- and Si NW- based Field-Effect-Transistors (FET) are able to deliver better performance than conventional devices, phonon scattering occurs. The goal of this research is to examine the phonon scattering effects on the performance of CNTFET and Si NWFET. The influence of phonon scattering is incorporated into the models by adding the transmission probability into the Landauer-Buttiker ballistic current equation. Results show that the phonon scattering effects have deteriorated the current and become significant with the increase of bias voltages. At ????=0.1??, the current of a CNTFET (Si NWFET) has 0.44% (15.2%) of reduction while at ????=0.8??, the current of a CNTFET (Si NWFET) has degraded by 6.5% (40%). There are two types of phonons, acoustic phonons and optical phonons, with different Mean Free Paths (MFP). The acoustic phonon is the primary cause of current reduction at a low gate bias (????=0.6??), while the optical phonon is dominant in reducing the current at a high gate bias. Besides, transistors with a short channel length operate close to the ballistic region, which is expected, as they approach the phonon MFP. In addition, the potential of CNTFET and Si NWFET to construct as logic gates is confirmed through Voltage Transfer Characteristic (VTC) by showing correct outputs for a given input. Moreover, the accuracy of the simulation results is assessed by comparing them with published models and experimental data, exhibiting good agreement with both. It is revealed that the use of a high-k dielectric and a thinner oxide are able to suppress the Short Channel Effects (SCE). Finally, it is experimentally proven that the device performance is improved by using a local bottom gate structure for CNTFET and a feedback FET for Si NWFET. |
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