Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination

Matrix inversion is a mathematical algorithm that is widely used and applied in many real time engineering applications. It is one of the most computational inten-sive and time consuming operations especially when it is performed in software. Gauss-Jordan Elimination is one of the many matrix invers...

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Main Author:	Oh, Eng Wei
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/54615/1/OhEngWeiMFKE2015.pdf
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id	my-utm-ep.54615
record_format	uketd_dc
spelling	my-utm-ep.546152020-10-21T00:42:50Z Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination 2015-06 Oh, Eng Wei TK Electrical engineering. Electronics Nuclear engineering Matrix inversion is a mathematical algorithm that is widely used and applied in many real time engineering applications. It is one of the most computational inten-sive and time consuming operations especially when it is performed in software. Gauss-Jordan Elimination is one of the many matrix inversion algorithms which has the advantage of using simpler mathematical operations to get the result. This work presents the architecture of a matrix inversion hardware using Gauss-Jordan Elimina-tion algorithm with single precision floating point representation. The proposed design is an enhancement of a previous work which implemented Gauss-Jordan Elimination to perform matrix inversion for complex matrix suitable for MIMO applications. The proposed design was bench-marked with other implementations such as hardware ar-chitecture of similar matrix inversion algorithm, hardware architecture of other matrix inversion algorithms and software implementation such as C++. The execution timing performance of the proposed design is improved in comparison with the previous ar-chitecture design by a factor of 0.14 for a matrix size of 36x36. Overall, the proposed design is capable of preforming matrix inversion for a matrix of size 36x36 in 1.9 milliseconds and consumes hardware resources of about 18128 logic elements. 2015-06 Thesis http://eprints.utm.my/id/eprint/54615/ http://eprints.utm.my/id/eprint/54615/1/OhEngWeiMFKE2015.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:86023 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Oh, Eng Wei Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
description	Matrix inversion is a mathematical algorithm that is widely used and applied in many real time engineering applications. It is one of the most computational inten-sive and time consuming operations especially when it is performed in software. Gauss-Jordan Elimination is one of the many matrix inversion algorithms which has the advantage of using simpler mathematical operations to get the result. This work presents the architecture of a matrix inversion hardware using Gauss-Jordan Elimina-tion algorithm with single precision floating point representation. The proposed design is an enhancement of a previous work which implemented Gauss-Jordan Elimination to perform matrix inversion for complex matrix suitable for MIMO applications. The proposed design was bench-marked with other implementations such as hardware ar-chitecture of similar matrix inversion algorithm, hardware architecture of other matrix inversion algorithms and software implementation such as C++. The execution timing performance of the proposed design is improved in comparison with the previous ar-chitecture design by a factor of 0.14 for a matrix size of 36x36. Overall, the proposed design is capable of preforming matrix inversion for a matrix of size 36x36 in 1.9 milliseconds and consumes hardware resources of about 18128 logic elements.
format	Thesis
qualification_level	Master's degree
author	Oh, Eng Wei
author_facet	Oh, Eng Wei
author_sort	Oh, Eng Wei
title	Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
title_short	Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
title_full	Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
title_fullStr	Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
title_full_unstemmed	Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination
title_sort	speed enhancement on a matrix inversion hardware architecture based on gauss-jordan elimination
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2015
url	http://eprints.utm.my/id/eprint/54615/1/OhEngWeiMFKE2015.pdf
_version_	1747817689222479872

Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination

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