Stream processor architecture – streaming memory system

Streaming memory system in this project is defined as a process of an stream processor that need to be able to stream whole chunk of data from/to external memory with real time performance. Real-time implementation of Convolution Neural Network (CNN) application are taking large amount of CPU cycle...

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Main Author:	Ngo, Wai Loon
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/54662/1/NgoWaiLoonMFKE2015.pdf
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id	my-utm-ep.54662
record_format	uketd_dc
spelling	my-utm-ep.546622020-11-03T07:38:41Z Stream processor architecture – streaming memory system 2015-06 Ngo, Wai Loon TK Electrical engineering. Electronics Nuclear engineering Streaming memory system in this project is defined as a process of an stream processor that need to be able to stream whole chunk of data from/to external memory with real time performance. Real-time implementation of Convolution Neural Network (CNN) application are taking large amount of CPU cycle to fetch and write data from/to external memory are popular issues in the field of media processing. So, a new FPGA-based streaming memory system was designed in order to allow the media processing application to execute multiple streaming operators. It would be a challenging task as computational capability would be increased. The hierarchy of streaming memory system consists of a memory system, stream register file (SRF) and arithmetic units. The memory system and SRF are the key part of the functional architecture of this project. This hierarchy can be used to exploit the parallelism and locality of streaming media applications. The main idea of three storage hierarchy is to allow the ALUs to operate efficiently in parallel. It is impractical to provide data on every cycle to ALU clusters using off-chip DRAM because peak bandwidth of memory system could not effectively support ALU clusters to achieve the computation rate. Moreover, the reason of creating streaming memory system is to fulfill the computational capability in media application that consists of multiple arithmetic operator. Two study case was tested which is RGB to YUV Cluster and 2D convolution cluster, and it was successfully to read or write a particular chunk of data in real time. 2015-06 Thesis http://eprints.utm.my/id/eprint/54662/ http://eprints.utm.my/id/eprint/54662/1/NgoWaiLoonMFKE2015.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:86720 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Ngo, Wai Loon Stream processor architecture – streaming memory system
description	Streaming memory system in this project is defined as a process of an stream processor that need to be able to stream whole chunk of data from/to external memory with real time performance. Real-time implementation of Convolution Neural Network (CNN) application are taking large amount of CPU cycle to fetch and write data from/to external memory are popular issues in the field of media processing. So, a new FPGA-based streaming memory system was designed in order to allow the media processing application to execute multiple streaming operators. It would be a challenging task as computational capability would be increased. The hierarchy of streaming memory system consists of a memory system, stream register file (SRF) and arithmetic units. The memory system and SRF are the key part of the functional architecture of this project. This hierarchy can be used to exploit the parallelism and locality of streaming media applications. The main idea of three storage hierarchy is to allow the ALUs to operate efficiently in parallel. It is impractical to provide data on every cycle to ALU clusters using off-chip DRAM because peak bandwidth of memory system could not effectively support ALU clusters to achieve the computation rate. Moreover, the reason of creating streaming memory system is to fulfill the computational capability in media application that consists of multiple arithmetic operator. Two study case was tested which is RGB to YUV Cluster and 2D convolution cluster, and it was successfully to read or write a particular chunk of data in real time.
format	Thesis
qualification_level	Master's degree
author	Ngo, Wai Loon
author_facet	Ngo, Wai Loon
author_sort	Ngo, Wai Loon
title	Stream processor architecture – streaming memory system
title_short	Stream processor architecture – streaming memory system
title_full	Stream processor architecture – streaming memory system
title_fullStr	Stream processor architecture – streaming memory system
title_full_unstemmed	Stream processor architecture – streaming memory system
title_sort	stream processor architecture – streaming memory system
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2015
url	http://eprints.utm.my/id/eprint/54662/1/NgoWaiLoonMFKE2015.pdf
_version_	1747817699471261696

Stream processor architecture – streaming memory system

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