Stream processor architecture – streaming memory system

Stream processor architecture – streaming memory system

Streaming memory system in this project is defined as a process of an stream processor that need to be able to stream whole chunk of data from/to external memory with real time performance. Real-time implementation of Convolution Neural Network (CNN) application are taking large amount of CPU cycle...

Saved in:

书目详细资料
主要作者:	Ngo, Wai Loon
格式:	Thesis
语言:	English
出版:	2015
主题:	TK Electrical engineering Electronics Nuclear engineering
在线阅读:	http://eprints.utm.my/id/eprint/54662/1/NgoWaiLoonMFKE2015.pdf
标签:	添加标签没有标签, 成为第一个标记此记录!

相似书籍

Design of the streaming processor architecture for microkernel controller and ALU
由: Anuar, Nuhairi
出版: (2015)

Evaluation of video streaming quality using quicktime streaming server (QTSS): a case study in Faculty of Information Technology & Quantitative Sciences, UiTM
由: Murli, Norhanifah
出版: (2005)

Analysis and design of stream cipher encryption algorithms
由: Tuan Mat, Tuan Sabri
出版: (1995)

Wireless communication for live digital video streaming applied in wireless LAN network
由: Mansor, Muhammad Muslim
出版: (2004)

Optimized cross layer design for video streaming over wireless local area network
由: Baguda, Yakubu Suleiman
出版: (2010)

Face verification system on digital signal processor
由: Yap, Wooi Hen
出版: (2008)

USB soft core with altera Nios processor
由: Cheah, Chee Teong
出版: (2007)

ARM processor emulator
由: Mohd. Hashim, Mohamad Hasruzairin
出版: (2015)

An efficient march (5n) FSM-based Memory Built-in Self-Test (MBIST) architecture with diagnosis capabilities
由: Ng, Kok Heng
出版: (2022)

A VLSI computing structure array processor
由: Loh, Sun Meng
出版: (1993)

Implementation of embedded in-circuit emulator for DLX processor
由: Bee Wooi, Khaw
出版: (2008)

Implementation of barrel shifter and multiplier for the DLX processor
由: Goh, Teng Sun
出版: (2008)

Low cost loosely coupled parallel processing system using standard processor
由: Awang Ahmad, Zahari
出版: (2009)

Multi-core 16-bit CPUs for PLC processor
由: Gan, Chi Qian
出版: (2022)

Development of a new arm processor evaluation board
由: Murugesu, Ganesan V.
出版: (2009)

A hardware implementation of Rivest-Shamir-Adleman co-processor for resource constrained embedded systems
由: Paniandi, Arul
出版: (2006)

Block-based neural network mapping on graphics processor unit
由: Ong, Chin Tong
出版: (2015)

Verilog design of input/output processor with built-in-self-test
由: Goh, Keng Hoo
出版: (2007)

An FPGA implementation of RSA processor core for public-key cryptosystem
由: Tan, Siang Lin
出版: (2001)

Instruction set simulator development for altera NIOS 2 processor
由: Teh, Fu Sun Ivan
出版: (2008)

Design of a route lookup processor for implementation in a FPGA-based system-on chip (SoC)
由: Teh , J-Wing
出版: (2004)

FPGA-based design of a math co-processor for the Amir CPU
由: Tan, Arthur Foo Yen
出版: (2020)

Fast fourier transform module for implementation in Nios II embedded processor
由: Ahmed, Hisham Azhari
出版: (2008)

Verilog design of bist on AES256 processor core with FPGA implementation
由: Hew, Kean Yung
出版: (2008)

RTL design of SHA-512 processor core for secure message hashing
由: Chua, Lee Ping
出版: (2008)

VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
由: Rajah, Avinash
出版: (2005)

Design of a lan interfacing module for a softcore processor AMIR CPU
由: Lim, Hui Teng
出版: (2020)

VHDL design of A 32-Bit RISC processor core for FPGA implementation
由: Marsono, Muhammad Nadzir
出版: (2001)

Integration of shape memory alloy for microactuation
由: Abuzaiter, Alaa A. H.
出版: (2016)

Implementation of direct torque control of brushless DC motor utilizing digital signal processor
由: Noor Azam, Ahmad Faiz
出版: (2015)

VHDL modelling and asic design of a shortest-path processor core for network routing
由: Teoh, Giap Seng
出版: (2003)

Memory subsystem of single board computer UTMSBC
由: Moh, Yun Hui
出版: (2008)

Long short-term memory autoencoder-based anomaly detection system for electric motors
由: Sharrar, Labib
出版: (2022)

Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
由: Ismail, Mohd. Izuan
出版: (2006)

Register transfer level design of compression processor core using verilog hardware description language
由: Mohd. Sabri, Roslee
出版: (2007)

The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL
由: Lim, Jonie Joo Nee
出版: (2008)

Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
由: Ooi, Tze Kian
出版: (2022)

Software-based self-test with scan design at register transfer level for 16-bit RISC processor
由: Ang, Kim Chuan
出版: (2010)

Design and implementation of 16 bit DSP core processor using field programmable gate array (FPGA)
由: Abdul Rahman, Abdul Aziz
出版: (2003)

RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P)
由: Liew, Meng Wei
出版: (2008)

Services hosted by the Perpustakaan Sultan Abdul Samad, Universiti Putra Malaysia with Cooperation MySyL Group