Verilog design of input/output processor with built-in-self-test

This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. Th...

全面介紹

Saved in:
書目詳細資料
主要作者: Goh, Keng Hoo
格式: Thesis
語言:English
出版: 2007
主題:
在線閱讀:http://eprints.utm.my/id/eprint/5959/1/GohKengHooMFKE2007.pdf
標簽: 添加標簽
沒有標簽, 成為第一個標記此記錄!