Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs

With growing developments in applications such as multimedia, technologies has pushed boundaries in the demands and popularity which used for a wide range of application domains. However, as complexity of development process of these applications that involve time-consuming and error-prone tasks inc...

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Main Author:	Sulaiman, Khalil Asyrani
Format:	Thesis
Language:	English
Published:	2016
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/60068/1/KhalilAsyraniSulaimanMFKE2016.pdf
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id	my-utm-ep.60068
record_format	uketd_dc
spelling	my-utm-ep.600682017-10-08T07:51:49Z Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs 2016-06 Sulaiman, Khalil Asyrani TK Electrical engineering. Electronics Nuclear engineering With growing developments in applications such as multimedia, technologies has pushed boundaries in the demands and popularity which used for a wide range of application domains. However, as complexity of development process of these applications that involve time-consuming and error-prone tasks increases, it is often scaled-up with development of the devices on the market to supports these applications. ORCC has helped in reducing the complexity of application developments by providing a set of modern tools based on dataflow programming. However, though Xronos generated HDLs has proven to be useful, yet it does not optimized to the resource utilization, power and timing analysis. It also yet to have a wide coverage across High-Level Synthesis (HLS) tools such as Altera Quartus and Synopsys Design Compiler. These coverages include the codes generated can be synthesize with other HDL tools. The critical part of this paper is generating of generic HDL for Altera Quartus or Synopsys Design Compiler from original HDL generated from ORCC and to provide co-simulation, automation environments for the RVC-CAL framework of Altera Quartus’s testbench by extracting simulation data that available from RVC-CAL framework, in which can be used to verify data from both ends (RVC-CAL’s and Quartus’s). Apart from that, in order to fully test generated code, comparison will be made with Xilinx Vivado HLS to benchmark functional test that are made with different HLS tools. This paper present the automation scripts that helps to produce better optimization of resource, power, and timing analysis from Xronos generated HDLs and providing automatic testbench that can be tested with Xilinx Vivado and other HDL tools. 2016-06 Thesis http://eprints.utm.my/id/eprint/60068/ http://eprints.utm.my/id/eprint/60068/1/KhalilAsyraniSulaimanMFKE2016.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:93921 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Sulaiman, Khalil Asyrani Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs
description	With growing developments in applications such as multimedia, technologies has pushed boundaries in the demands and popularity which used for a wide range of application domains. However, as complexity of development process of these applications that involve time-consuming and error-prone tasks increases, it is often scaled-up with development of the devices on the market to supports these applications. ORCC has helped in reducing the complexity of application developments by providing a set of modern tools based on dataflow programming. However, though Xronos generated HDLs has proven to be useful, yet it does not optimized to the resource utilization, power and timing analysis. It also yet to have a wide coverage across High-Level Synthesis (HLS) tools such as Altera Quartus and Synopsys Design Compiler. These coverages include the codes generated can be synthesize with other HDL tools. The critical part of this paper is generating of generic HDL for Altera Quartus or Synopsys Design Compiler from original HDL generated from ORCC and to provide co-simulation, automation environments for the RVC-CAL framework of Altera Quartus’s testbench by extracting simulation data that available from RVC-CAL framework, in which can be used to verify data from both ends (RVC-CAL’s and Quartus’s). Apart from that, in order to fully test generated code, comparison will be made with Xilinx Vivado HLS to benchmark functional test that are made with different HLS tools. This paper present the automation scripts that helps to produce better optimization of resource, power, and timing analysis from Xronos generated HDLs and providing automatic testbench that can be tested with Xilinx Vivado and other HDL tools.
format	Thesis
qualification_level	Master's degree
author	Sulaiman, Khalil Asyrani
author_facet	Sulaiman, Khalil Asyrani
author_sort	Sulaiman, Khalil Asyrani
title	Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs
title_short	Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs
title_full	Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs
title_fullStr	Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs
title_full_unstemmed	Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs
title_sort	automation scripts for generic synthesis and co-simulation for xronos generated hdls
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2016
url	http://eprints.utm.my/id/eprint/60068/1/KhalilAsyraniSulaimanMFKE2016.pdf
_version_	1747817755024818176

Automation scripts for generic synthesis and co-simulation for Xronos generated HDLs

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