Ch'ng, H. S. (2007). Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing.
توثيق أسلوب شيكاغو (الطبعة السابعة عشر)Ch'ng, Heng Sun. Graph Processing Hardware Accelerator for Shortest Path Algorithms in Nanometer Very Large-scale Integration Interconnect Routing. 2007.
توثيق جمعية اللغة المعاصرة MLA (الطبعة الثامنة)Ch'ng, Heng Sun. Graph Processing Hardware Accelerator for Shortest Path Algorithms in Nanometer Very Large-scale Integration Interconnect Routing. 2007.
تحذير: قد لا تكون هذه الاستشهادات دائما دقيقة بنسبة 100%.