Ch'ng, H. S. (2007). Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing.
Chicago Style (17th ed.) CitationCh'ng, Heng Sun. Graph Processing Hardware Accelerator for Shortest Path Algorithms in Nanometer Very Large-scale Integration Interconnect Routing. 2007.
MLA (8th ed.) CitationCh'ng, Heng Sun. Graph Processing Hardware Accelerator for Shortest Path Algorithms in Nanometer Very Large-scale Integration Interconnect Routing. 2007.
Warning: These citations may not always be 100% accurate.