Verilog design of a 256-bit AES crypto processor core

Verilog design of a 256-bit AES crypto processor core

The 21st Century is the Century of Digital, almost all of the information processing and telecommunication are in digital formats, therefore it is a must to ensure the digital data storage and transmission are secured, thus to ensure privacy. Cryptography is the practice to protect oneâ€™s informati...

Saved in:

書目詳細資料
主要作者:	Lai, Yit Pin
格式:	Thesis
語言:	English
出版:	2007
主題:	TK Electrical engineering Electronics Nuclear engineering QA76 Computer software
在線閱讀:	http://eprints.utm.my/id/eprint/6392/1/LaiYitPinMFKE2007.pdf
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

相似書籍

Verilog design of bist on AES256 processor core with FPGA implementation
由: Hew, Kean Yung
出版: (2008)

Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
由: Ismail, Mohd. Izuan
出版: (2006)

The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL
由: Lim, Jonie Joo Nee
出版: (2008)

Register transfer level design of compression processor core using verilog hardware description language
由: Mohd. Sabri, Roslee
出版: (2007)

Verilog design of input/output processor with built-in-self-test
由: Goh, Keng Hoo
出版: (2007)

Multi-core 16-bit CPUs for PLC processor
由: Gan, Chi Qian
出版: (2022)

VHDL design of A 32-Bit RISC processor core for FPGA implementation
由: Marsono, Muhammad Nadzir
出版: (2001)

Design and implementation of 16 bit DSP core processor using field programmable gate array (FPGA)
由: Abdul Rahman, Abdul Aziz
出版: (2003)

RISC Design: Synthesis Of The MIPS Processor Core
由: Yew, Teong Guan
出版: (2003)

The RTL design of 32-bit RISC processor using verilog HDL
由: Manab, Hafizul Hasni
出版: (2012)

USB soft core with altera Nios processor
由: Cheah, Chee Teong
出版: (2007)

Real-time FPGA implementation of baseline JPEG codec processor core
由: Suleiman, Ishak
出版: (2002)

RTL design of SHA-512 processor core for secure message hashing
由: Chua, Lee Ping
出版: (2008)

Software-based self-test with scan design at register transfer level for 16-bit RISC processor
由: Ang, Kim Chuan
出版: (2010)

VHDL modelling and asic design of a shortest-path processor core for network routing
由: Teoh, Giap Seng
出版: (2003)

An FPGA implementation of RSA processor core for public-key cryptosystem
由: Tan, Siang Lin
出版: (2001)

Verilog modelling of Modbus TCP at 100 mbps
由: Tan, Zhe Jie
出版: (2022)

RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P)
由: Liew, Meng Wei
出版: (2008)

An embedded cryptosystem implementing symmetric cipher and public-key crypto algorithms in hardware
由: Hau, Yuan Wen
出版: (2005)

Modeling and simulation of graphene three branch junction using verilog-A
由: Chin, Ee Mei
出版: (2015)

Agile development of kiosk summon payment application in automated enforcement system( AES)
由: Darban, Ehsan Alah Abaszadeh,
出版: (2013)

Securing cloud data system (SCDS) for key exposure using AES algorithm
由: Thabet Albatol, Mohammed Samer Hasan
出版: (2021)

Design of a hash processor chip and the implementation of a digital signature subsystem for data security
由: Chong, Wei Sheng
出版: (2002)

Software-based self-testing for a risc processor
由: Teh, Wee Meng
出版: (2014)

Analysis of FPGA design methods using AN 8 BIT ALU
由: Mohd Zin, Rosnah
出版: (2005)

Design of the streaming processor architecture for microkernel controller and ALU
由: Anuar, Nuhairi
出版: (2015)

Performance comparison analysis of aes-256 sha-256-hmac, aes-256 md5-hmac, 3des sha-256-hmac and 3des-md5-hmac on ipsec vpn using gns3 / Mohd Hilman Lukman
由: Lukman, Mohd Hilman
出版: (2016)

Cache-Aware Multi-Core Operating System Scheduler Design
由: Lam, Jun Wei
出版: (2009)

Spiral bit-map signature for content-based images retrieval
由: Wang, Hui Hui
出版: (2003)

ARM processor emulator
由: Mohd. Hashim, Mohamad Hasruzairin
出版: (2015)

FPGA-based design of a math co-processor for the Amir CPU
由: Tan, Arthur Foo Yen
出版: (2020)

Digital image watermarking by using intermediate significant bits in gray scale images
由: Sharifara, Ali
出版: (2012)

Studies On A Power Signal Processor For Power Supply Quality Assessment
由: Kanaesalingam, Shri Rajini Kanth
出版: (2007)

VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm
由: Rajah, Avinash
出版: (2005)

Design of a lan interfacing module for a softcore processor AMIR CPU
由: Lim, Hui Teng
出版: (2020)

Design and construction of GMSK bit error rate measurement system for PCN applications
由: Syed Yusof, Sharifah Kamilah
出版: (1994)

Computer-based Malay stuttering assessment system
由: Ooi, Chia Ai
出版: (2007)

Simulation of hybrid stepping motor using matlab-simulink
由: Mohamad Idris, Rasyidah
出版: (2003)

Speed Efficient Hardware Implementation Of Advanced Encryption Standard (Aes)
由: Low, Chiau Thian
出版: (2017)

A VLSI computing structure array processor
由: Loh, Sun Meng
出版: (1993)

Services hosted by the Perpustakaan Sultan Abdul Samad, Universiti Putra Malaysia with Cooperation MySyL Group