Test vectors reductoin for integrated circuit testing using horizontal hamming distance

In testing digital combinational logic for stuck-at faults, it is required to determine the most appropriate test sequence needed to detect the required number of possible faults. The exhaustive test pattern generation method is the simplest approach to implement as it produces test patterns consist...

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Main Author:	Alamgir, Arbab
Format:	Thesis
Language:	English
Published:	2016
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/77590/1/ArbabAlamgirMFKE2016.pdf
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spelling	my-utm-ep.775902018-06-25T08:55:10Z Test vectors reductoin for integrated circuit testing using horizontal hamming distance 2016-06 Alamgir, Arbab TK Electrical engineering. Electronics Nuclear engineering In testing digital combinational logic for stuck-at faults, it is required to determine the most appropriate test sequence needed to detect the required number of possible faults. The exhaustive test pattern generation method is the simplest approach to implement as it produces test patterns consisting of all possible input combinations of the circuit under test. However, a consequence of this approach is that it results in a large test set when the number of circuit inputs is large. This can take an unnecessarily long time to apply on the circuit under test as during the test process, only a small fraction of all possible test vectors is actually required to produce high percentage of fault coverage. As an alternative, random test pattern generation applies a random set of test patterns which can be used to reduce the number of test patterns compared to exhaustive test. However, both test pattern generation approaches generate unnecessary test vectors to apply to the circuit as multiple patterns typically detect the same fault. Antirandom testing on the other hand ensures that the identified test vectors to use do not detect the same fault by introducing the concept of Hamming distance between test vectors and this distance is be maximized. This results in a reduction in the number of required test vectors when compared to an exhaustive test. However, the algorithm for Antirandom test vector generation is computation intensive and vague in its definition when there are more than one possible next test vectors. In this study, efficient calculation of Hamming distance has been proposed, moreover the choice of the next test vector is addressed by using the proposed Horizontal Hamming distance method which has not yet been explored. The approach effectively detects faults at a much faster rate and produces a much higher fault coverage than the existing Antirandom method. 2016-06 Thesis http://eprints.utm.my/id/eprint/77590/ http://eprints.utm.my/id/eprint/77590/1/ArbabAlamgirMFKE2016.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:94131 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Alamgir, Arbab Test vectors reductoin for integrated circuit testing using horizontal hamming distance
description	In testing digital combinational logic for stuck-at faults, it is required to determine the most appropriate test sequence needed to detect the required number of possible faults. The exhaustive test pattern generation method is the simplest approach to implement as it produces test patterns consisting of all possible input combinations of the circuit under test. However, a consequence of this approach is that it results in a large test set when the number of circuit inputs is large. This can take an unnecessarily long time to apply on the circuit under test as during the test process, only a small fraction of all possible test vectors is actually required to produce high percentage of fault coverage. As an alternative, random test pattern generation applies a random set of test patterns which can be used to reduce the number of test patterns compared to exhaustive test. However, both test pattern generation approaches generate unnecessary test vectors to apply to the circuit as multiple patterns typically detect the same fault. Antirandom testing on the other hand ensures that the identified test vectors to use do not detect the same fault by introducing the concept of Hamming distance between test vectors and this distance is be maximized. This results in a reduction in the number of required test vectors when compared to an exhaustive test. However, the algorithm for Antirandom test vector generation is computation intensive and vague in its definition when there are more than one possible next test vectors. In this study, efficient calculation of Hamming distance has been proposed, moreover the choice of the next test vector is addressed by using the proposed Horizontal Hamming distance method which has not yet been explored. The approach effectively detects faults at a much faster rate and produces a much higher fault coverage than the existing Antirandom method.
format	Thesis
qualification_level	Master's degree
author	Alamgir, Arbab
author_facet	Alamgir, Arbab
author_sort	Alamgir, Arbab
title	Test vectors reductoin for integrated circuit testing using horizontal hamming distance
title_short	Test vectors reductoin for integrated circuit testing using horizontal hamming distance
title_full	Test vectors reductoin for integrated circuit testing using horizontal hamming distance
title_fullStr	Test vectors reductoin for integrated circuit testing using horizontal hamming distance
title_full_unstemmed	Test vectors reductoin for integrated circuit testing using horizontal hamming distance
title_sort	test vectors reductoin for integrated circuit testing using horizontal hamming distance
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2016
url	http://eprints.utm.my/id/eprint/77590/1/ArbabAlamgirMFKE2016.pdf
_version_	1747817784447860736

Test vectors reductoin for integrated circuit testing using horizontal hamming distance

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