Hybrid constraint-based test pattern generation

The role of testing in Integrated circuit (IC) is to determine the correctness of manufactured circuits. Therefore, testing is important since the fraction of good chips sold in the market yields the quality of the product. Automatic test equipment (ATE) is equipment that used in manufacturing test....

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Main Author:	Abdullah, Ayub Chin
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/78117/1/AyubChinAbdullahMFKE20131.pdf
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id	my-utm-ep.78117
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spelling	my-utm-ep.781172018-07-25T08:17:35Z Hybrid constraint-based test pattern generation 2013-06 Abdullah, Ayub Chin TK Electrical engineering. Electronics Nuclear engineering The role of testing in Integrated circuit (IC) is to determine the correctness of manufactured circuits. Therefore, testing is important since the fraction of good chips sold in the market yields the quality of the product. Automatic test equipment (ATE) is equipment that used in manufacturing test. The advance in IC technology make the memory needed for ATE is big. However, this could be lessened by reducing the data volume inserted in the ATE. This could be achieved through test compaction like fault collapsing. In this research, hybrid constraint-based test pattern generation proposed that include fault injection, Automatic test pattern generation (ATPG) and fault simulation. The fault injection is creating the faulty circuits while the ATPG searching the test patterns. For the fault simulation, it calculates the fault coverage of the ATPG system. In the fault injection, the functional fault modeling adopted which applied the fault collapsing. This fault collapsing is aiding in test compaction. Five experiments being done on eight Circuit under tests (CUTs) from the International Torino Conference (ITC) '99 benchmark circuits. The high-level and gate-level fault coverage, and the test length for this CUTs have been obtained from this experiments. The average of compaction ratio that obtained by the proposed method is 5.42%. 2013-06 Thesis http://eprints.utm.my/id/eprint/78117/ http://eprints.utm.my/id/eprint/78117/1/AyubChinAbdullahMFKE20131.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:78613 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Abdullah, Ayub Chin Hybrid constraint-based test pattern generation
description	The role of testing in Integrated circuit (IC) is to determine the correctness of manufactured circuits. Therefore, testing is important since the fraction of good chips sold in the market yields the quality of the product. Automatic test equipment (ATE) is equipment that used in manufacturing test. The advance in IC technology make the memory needed for ATE is big. However, this could be lessened by reducing the data volume inserted in the ATE. This could be achieved through test compaction like fault collapsing. In this research, hybrid constraint-based test pattern generation proposed that include fault injection, Automatic test pattern generation (ATPG) and fault simulation. The fault injection is creating the faulty circuits while the ATPG searching the test patterns. For the fault simulation, it calculates the fault coverage of the ATPG system. In the fault injection, the functional fault modeling adopted which applied the fault collapsing. This fault collapsing is aiding in test compaction. Five experiments being done on eight Circuit under tests (CUTs) from the International Torino Conference (ITC) '99 benchmark circuits. The high-level and gate-level fault coverage, and the test length for this CUTs have been obtained from this experiments. The average of compaction ratio that obtained by the proposed method is 5.42%.
format	Thesis
qualification_level	Master's degree
author	Abdullah, Ayub Chin
author_facet	Abdullah, Ayub Chin
author_sort	Abdullah, Ayub Chin
title	Hybrid constraint-based test pattern generation
title_short	Hybrid constraint-based test pattern generation
title_full	Hybrid constraint-based test pattern generation
title_fullStr	Hybrid constraint-based test pattern generation
title_full_unstemmed	Hybrid constraint-based test pattern generation
title_sort	hybrid constraint-based test pattern generation
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2013
url	http://eprints.utm.my/id/eprint/78117/1/AyubChinAbdullahMFKE20131.pdf
_version_	1747817911146250240

Hybrid constraint-based test pattern generation

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