Interconnect tree optimization algorithm in nanometer very large scale integration designs

Interconnect tree optimization algorithm in nanometer very large scale integration designs

This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant f...

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书目详细资料
主要作者:	Eh Kan, Chessda Uttraphan
格式:	Thesis
语言:	English
出版:	2016
主题:	TK Electrical engineering Electronics Nuclear engineering
在线阅读:	http://eprints.utm.my/id/eprint/78709/1/ChessdaUttraphanEhPFKE2016.pdf
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