Digital logic circuit design using adiabatic approach

A major challenge for the circuit designers nowadays is to meet the demand for low power, especially those used in portable and wearable devices which have limited energy power supply. The reasons of designing low power consumption circuit are to reduce energy usage and minimize dissipation of heat....

Full description

Saved in:

Bibliographic Details
Main Author:	Zainal Abidin, Nurul Aisyah Nadiah
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/78950/1/NurulAisyahNadiahMFKE2017.pdf
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my-utm-ep.78950
record_format	uketd_dc
spelling	my-utm-ep.789502018-09-19T05:12:54Z Digital logic circuit design using adiabatic approach 2017-05 Zainal Abidin, Nurul Aisyah Nadiah TK Electrical engineering. Electronics Nuclear engineering A major challenge for the circuit designers nowadays is to meet the demand for low power, especially those used in portable and wearable devices which have limited energy power supply. The reasons of designing low power consumption circuit are to reduce energy usage and minimize dissipation of heat. Adiabatic technique is an attractive approach to obtain power optimization where some of the charge in capacitance can be recycled instead of being dissipated as heat. In this thesis, a methodology for designing sequential adiabatic circuits employing a single-phase power clock was investigated. Initially, methods to simulate dynamic power were analysed by identifying a better and reliable method to simulate adiabatic dynamic power. In addition, a method to validate the output voltage swing was presented. The relationship between voltage swing and power dissipation was analysed. Then, several adiabatic sequential D flip flops (DFF) designs which make use of combinational adiabatic circuit design based on quasi-adiabatic were proposed and suitable types of alternating current power supply which influence dynamic power were analysed and selected. The functionality and performance of the proposed circuits were compared against other adiabatic and traditional Complimentary Metal-Oxide Semiconductor (CMOS) circuits and verified to function up to 1 GHz operating region. Besides the circuits, the layout of the proposed sequential adiabatic design was also produced. All simulations were carried out using 0.25 ^m CMOS technology parameters using Tanner Electronic Design Aided and HSPICE tools. The findings showed that the proposed combinational circuit had less transistor count, lower power dissipation with lower voltage swing as compared to reference adiabatic circuits. Furthermore, the proposed sequential DFF circuit showed 25% less power dissipation compared to traditional CMOS. 2017-05 Thesis http://eprints.utm.my/id/eprint/78950/ http://eprints.utm.my/id/eprint/78950/1/NurulAisyahNadiahMFKE2017.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:109561 phd doctoral Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Zainal Abidin, Nurul Aisyah Nadiah Digital logic circuit design using adiabatic approach
description	A major challenge for the circuit designers nowadays is to meet the demand for low power, especially those used in portable and wearable devices which have limited energy power supply. The reasons of designing low power consumption circuit are to reduce energy usage and minimize dissipation of heat. Adiabatic technique is an attractive approach to obtain power optimization where some of the charge in capacitance can be recycled instead of being dissipated as heat. In this thesis, a methodology for designing sequential adiabatic circuits employing a single-phase power clock was investigated. Initially, methods to simulate dynamic power were analysed by identifying a better and reliable method to simulate adiabatic dynamic power. In addition, a method to validate the output voltage swing was presented. The relationship between voltage swing and power dissipation was analysed. Then, several adiabatic sequential D flip flops (DFF) designs which make use of combinational adiabatic circuit design based on quasi-adiabatic were proposed and suitable types of alternating current power supply which influence dynamic power were analysed and selected. The functionality and performance of the proposed circuits were compared against other adiabatic and traditional Complimentary Metal-Oxide Semiconductor (CMOS) circuits and verified to function up to 1 GHz operating region. Besides the circuits, the layout of the proposed sequential adiabatic design was also produced. All simulations were carried out using 0.25 ^m CMOS technology parameters using Tanner Electronic Design Aided and HSPICE tools. The findings showed that the proposed combinational circuit had less transistor count, lower power dissipation with lower voltage swing as compared to reference adiabatic circuits. Furthermore, the proposed sequential DFF circuit showed 25% less power dissipation compared to traditional CMOS.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Zainal Abidin, Nurul Aisyah Nadiah
author_facet	Zainal Abidin, Nurul Aisyah Nadiah
author_sort	Zainal Abidin, Nurul Aisyah Nadiah
title	Digital logic circuit design using adiabatic approach
title_short	Digital logic circuit design using adiabatic approach
title_full	Digital logic circuit design using adiabatic approach
title_fullStr	Digital logic circuit design using adiabatic approach
title_full_unstemmed	Digital logic circuit design using adiabatic approach
title_sort	digital logic circuit design using adiabatic approach
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2017
url	http://eprints.utm.my/id/eprint/78950/1/NurulAisyahNadiahMFKE2017.pdf
_version_	1747818111265931264

Digital logic circuit design using adiabatic approach

Similar Items