Clustered two-dimensional mesh topology for large-scale network-on-chip architecture
Driven by the continuous scaling of Moore’s law, the number of processing cores in chip multiprocessors and systems-on-a-chip are expected to grow tremendously in the near future. Connecting the different components of a multiprocessor chip in a scalable and efficient way has become increasingly cha...
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2017
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| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/79138/1/MehdiBaboliPFKE2017.pdf |
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| 總結: | Driven by the continuous scaling of Moore’s law, the number of processing cores in chip multiprocessors and systems-on-a-chip are expected to grow tremendously in the near future. Connecting the different components of a multiprocessor chip in a scalable and efficient way has become increasingly challenging. Current network-on-chip (NoC) topologies are adequate for small-size networks but are not optimized for large-scale networks. Transmitted packets inside a large NoC require longer route to reach their destinations, resulting in an increase in certain performance parameters such as latency and power consumption. Thus, it is necessary to develop a new topology appropriate for large-size NoCs. In this research, we proposed a cost-effective network topology for large-size NoCs that improves performance in terms of end-to-end latency. The topology, called RaMesh, consists of clusters of mesh networks. A routing algorithm suitable for this topology was also proposed. The RaMesh architecture together with mesh, torus, and clustered 2D-mesh were simulated using Noxim (NoC simulator), C for software NoC models, and Altera ModelSim for Verilog hardware models. Simulations were conducted under different network traffic and for a variety of network sizes. Experimental results showed that RaMesh performed better than equivalent 2D-mesh and torus topologies. RaMesh topology was also benchmarked against a clustered mesh topology. Average hop count in the proposed topology was at least 22.7% lower compared to the mesh and torus. Average latency was also decreased by at least 24.66% as compared to the mesh and torus. Finally, the saturation point for the proposed topology increased by at least 15% as compared to mesh and torus. |
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