Register-transfer level design of sum of absolute transformed difference for high efficiency video coding

High Efficiency Video Coding (HEVC) is the state-of-the-art video coding standard which offers 50% improvement in coding efficiency over its predecessor Advanced Video Coding (AVC). Compared to AVC, HEVC supports up to 33 angular modes, DC mode and planar mode. The significant rise in the number of...

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Main Author:	Heh, Whit Ney
Format:	Thesis
Language:	English
Published:	2018
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/79316/1/HehWhitNeyMFKE2018.pdf
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id	my-utm-ep.79316
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spelling	my-utm-ep.793162018-10-14T08:42:17Z Register-transfer level design of sum of absolute transformed difference for high efficiency video coding 2018 Heh, Whit Ney TK Electrical engineering. Electronics Nuclear engineering High Efficiency Video Coding (HEVC) is the state-of-the-art video coding standard which offers 50% improvement in coding efficiency over its predecessor Advanced Video Coding (AVC). Compared to AVC, HEVC supports up to 33 angular modes, DC mode and planar mode. The significant rise in the number of intra prediction mode however has increased the computational complexity. Sum of Absolute Transformed Difference (SATD), a fast Rate Distortion Optimization (RDO) intra prediction algorithm in the HEVC standard, is one of the most complex and compute-intensive part of the encoding process. SATD alone can takes up to 40% of the total encoding time; hence off-loading it to dedicated hardware accelerators is necessary to address the increasing need for real-time video coding in accordance with the push for coding efficiency. This work proposes a Verilog-described N × N SATD hardware architecture which is based on Hadamard Transform. The architecture would support a variable block size from 4 × 4 to 32 × 32 with 1-D horizontal and 1-D vertical Hadamard Transform. At the same time, it is designed to achieve throughput optimization by pipelining and feedthrough control. The performance of the implemented SATD is then evaluated in terms of utilization, timing and power. 2018 Thesis http://eprints.utm.my/id/eprint/79316/ http://eprints.utm.my/id/eprint/79316/1/HehWhitNeyMFKE2018.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Heh, Whit Ney Register-transfer level design of sum of absolute transformed difference for high efficiency video coding
description	High Efficiency Video Coding (HEVC) is the state-of-the-art video coding standard which offers 50% improvement in coding efficiency over its predecessor Advanced Video Coding (AVC). Compared to AVC, HEVC supports up to 33 angular modes, DC mode and planar mode. The significant rise in the number of intra prediction mode however has increased the computational complexity. Sum of Absolute Transformed Difference (SATD), a fast Rate Distortion Optimization (RDO) intra prediction algorithm in the HEVC standard, is one of the most complex and compute-intensive part of the encoding process. SATD alone can takes up to 40% of the total encoding time; hence off-loading it to dedicated hardware accelerators is necessary to address the increasing need for real-time video coding in accordance with the push for coding efficiency. This work proposes a Verilog-described N × N SATD hardware architecture which is based on Hadamard Transform. The architecture would support a variable block size from 4 × 4 to 32 × 32 with 1-D horizontal and 1-D vertical Hadamard Transform. At the same time, it is designed to achieve throughput optimization by pipelining and feedthrough control. The performance of the implemented SATD is then evaluated in terms of utilization, timing and power.
format	Thesis
qualification_level	Master's degree
author	Heh, Whit Ney
author_facet	Heh, Whit Ney
author_sort	Heh, Whit Ney
title	Register-transfer level design of sum of absolute transformed difference for high efficiency video coding
title_short	Register-transfer level design of sum of absolute transformed difference for high efficiency video coding
title_full	Register-transfer level design of sum of absolute transformed difference for high efficiency video coding
title_fullStr	Register-transfer level design of sum of absolute transformed difference for high efficiency video coding
title_full_unstemmed	Register-transfer level design of sum of absolute transformed difference for high efficiency video coding
title_sort	register-transfer level design of sum of absolute transformed difference for high efficiency video coding
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2018
url	http://eprints.utm.my/id/eprint/79316/1/HehWhitNeyMFKE2018.pdf
_version_	1747818198699343872

Register-transfer level design of sum of absolute transformed difference for high efficiency video coding

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