Face detection hardware accelerator using C-based high-level synthesis

Face detection hardware accelerator using C-based high-level synthesis

Research has shown that Field Programmable Gate Array (FPGA) based implementation of image processing system results in high computational speed and energy efficiency. However, FPGA design has relatively long development time compared to alternative implementation platforms, such as those based on C...

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書目詳細資料
主要作者:	Yeap, Han Chien
格式:	Thesis
語言:	English
出版:	2018
主題:	TK Electrical engineering Electronics Nuclear engineering
在線閱讀:	http://eprints.utm.my/id/eprint/79563/1/Yeap%2C%20Han%20Chien.pdf
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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