Low noise and low power ECG amplifier using cmos 0.13μm technology

Through the scaling down of modern VLSI technologies, the realization of CMOS based electrocardiogram (ECG) device becoming wearable to its user is possible. Yet, this transition introduces more constraints to its analog circuits. This is due to the measured electrical signal of ECG devices, or know...

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Main Author:	Kamaruzzaman, Zulfadli
Format:	Thesis
Language:	English
Published:	2018
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/79603/1/ZulfadliKamaruzzamanPFKE2018.pdf
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id	my-utm-ep.79603
record_format	uketd_dc
spelling	my-utm-ep.796032018-10-31T13:01:08Z Low noise and low power ECG amplifier using cmos 0.13μm technology 2018 Kamaruzzaman, Zulfadli TK Electrical engineering. Electronics Nuclear engineering Through the scaling down of modern VLSI technologies, the realization of CMOS based electrocardiogram (ECG) device becoming wearable to its user is possible. Yet, this transition introduces more constraints to its analog circuits. This is due to the measured electrical signal of ECG devices, or known as ECG signal possessed characteristics that are low in frequency (0.1 to 150Hz) and amplitude (<5mV), thus it lead to every ECG devices suffered from flicker noise for low frequency cardiac signal acquisition at the front-end of its sensor, 50 Hz power line electromagnetic interference, and the large unstable input offsets due to the improper attachment of electrode-skin interface. Therefore, to encounter this problem, the frontend of ECG devices, which is amplifier needed to be enhance so it able to accurately detect the ECG signals. Besides that, the amplifier must able to operate at low voltage and less power consumption so that it can be used in wearable device. In this work, a high performance CMOS amplifier for ECG sensors that improves the noise issue and suitable for low power wearable cardiac screening is designed. The designed circuit adopts the folded cascode topology to achieve high gain and less susceptible to noise. This work uses 0.13 μm CMOS process technology from Silterra and Mentor Graphics Pyxis as the design tool. This successfully achieve high CMRR which is 160dB. Besides that, this work also able to reduce the noise at the front-end amplifier system down to 1.28nV/√Hz. The power consumption of the designed amplifier is 3 μW, which is low and suitable to be implemented on design for wearable ECG devices. 2018 Thesis http://eprints.utm.my/id/eprint/79603/ http://eprints.utm.my/id/eprint/79603/1/ZulfadliKamaruzzamanPFKE2018.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Kamaruzzaman, Zulfadli Low noise and low power ECG amplifier using cmos 0.13μm technology
description	Through the scaling down of modern VLSI technologies, the realization of CMOS based electrocardiogram (ECG) device becoming wearable to its user is possible. Yet, this transition introduces more constraints to its analog circuits. This is due to the measured electrical signal of ECG devices, or known as ECG signal possessed characteristics that are low in frequency (0.1 to 150Hz) and amplitude (<5mV), thus it lead to every ECG devices suffered from flicker noise for low frequency cardiac signal acquisition at the front-end of its sensor, 50 Hz power line electromagnetic interference, and the large unstable input offsets due to the improper attachment of electrode-skin interface. Therefore, to encounter this problem, the frontend of ECG devices, which is amplifier needed to be enhance so it able to accurately detect the ECG signals. Besides that, the amplifier must able to operate at low voltage and less power consumption so that it can be used in wearable device. In this work, a high performance CMOS amplifier for ECG sensors that improves the noise issue and suitable for low power wearable cardiac screening is designed. The designed circuit adopts the folded cascode topology to achieve high gain and less susceptible to noise. This work uses 0.13 μm CMOS process technology from Silterra and Mentor Graphics Pyxis as the design tool. This successfully achieve high CMRR which is 160dB. Besides that, this work also able to reduce the noise at the front-end amplifier system down to 1.28nV/√Hz. The power consumption of the designed amplifier is 3 μW, which is low and suitable to be implemented on design for wearable ECG devices.
format	Thesis
qualification_level	Master's degree
author	Kamaruzzaman, Zulfadli
author_facet	Kamaruzzaman, Zulfadli
author_sort	Kamaruzzaman, Zulfadli
title	Low noise and low power ECG amplifier using cmos 0.13μm technology
title_short	Low noise and low power ECG amplifier using cmos 0.13μm technology
title_full	Low noise and low power ECG amplifier using cmos 0.13μm technology
title_fullStr	Low noise and low power ECG amplifier using cmos 0.13μm technology
title_full_unstemmed	Low noise and low power ECG amplifier using cmos 0.13μm technology
title_sort	low noise and low power ecg amplifier using cmos 0.13μm technology
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2018
url	http://eprints.utm.my/id/eprint/79603/1/ZulfadliKamaruzzamanPFKE2018.pdf
_version_	1747818266784432128

Low noise and low power ECG amplifier using cmos 0.13μm technology

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