Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller

Convolution Neural Network (CNN) is a special kind of neural network that is inspired by the behaviour of optic nerves in living creatures. CNN is gaining more and more attention nowadays because of the increased demand for high speed and lowcost synthetic vision systems. However, CNN can be both co...

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Main Author:	Mohammed, Mohammed Isam Eldin Hassan
Format:	Thesis
Language:	English
Published:	2020
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/92997/1/MohammedIsamEldinMSKE2020.pdf
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id	my-utm-ep.92997
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spelling	my-utm-ep.929972021-11-07T06:00:17Z Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller 2020 Mohammed, Mohammed Isam Eldin Hassan TK Electrical engineering. Electronics Nuclear engineering Convolution Neural Network (CNN) is a special kind of neural network that is inspired by the behaviour of optic nerves in living creatures. CNN is gaining more and more attention nowadays because of the increased demand for high speed and lowcost synthetic vision systems. However, CNN can be both compute- and memoryintensive. For that reason, implementation in a general-purpose processor will be slow and inefficient. Therefore, this project proposes a flexible CNN hardware accelerator that targets the Field Programmable Gate Array (FPGA) platform and features an optimized memory controller to reduce redundancy memory access. The main advantage of this project is that the accelerator is flexible - meaning that the user of the accelerator has the capability of modifying the architecture using parameterization to optimize for execution speed, resource utilization, and power consumption. The accelerator employs various hardware design techniques like loop unrolling, pipelining, optimized memory controller, and others to achieve the targeted performance. The accelerator is written in System Verilog language using Xilinx’s Vivado software and is tested using a single convolution layer from several selected CNN architectures. Then, it is compared against the same convolution layer implemented in Matlab. The proposed accelerator shows a huge speedup compared to the software counterpart of up to 4251X speed up with reasonable resource utilization and consumes only 0.27 W per layer. 2020 Thesis http://eprints.utm.my/id/eprint/92997/ http://eprints.utm.my/id/eprint/92997/1/MohammedIsamEldinMSKE2020.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135883 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Mohammed, Mohammed Isam Eldin Hassan Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
description	Convolution Neural Network (CNN) is a special kind of neural network that is inspired by the behaviour of optic nerves in living creatures. CNN is gaining more and more attention nowadays because of the increased demand for high speed and lowcost synthetic vision systems. However, CNN can be both compute- and memoryintensive. For that reason, implementation in a general-purpose processor will be slow and inefficient. Therefore, this project proposes a flexible CNN hardware accelerator that targets the Field Programmable Gate Array (FPGA) platform and features an optimized memory controller to reduce redundancy memory access. The main advantage of this project is that the accelerator is flexible - meaning that the user of the accelerator has the capability of modifying the architecture using parameterization to optimize for execution speed, resource utilization, and power consumption. The accelerator employs various hardware design techniques like loop unrolling, pipelining, optimized memory controller, and others to achieve the targeted performance. The accelerator is written in System Verilog language using Xilinx’s Vivado software and is tested using a single convolution layer from several selected CNN architectures. Then, it is compared against the same convolution layer implemented in Matlab. The proposed accelerator shows a huge speedup compared to the software counterpart of up to 4251X speed up with reasonable resource utilization and consumes only 0.27 W per layer.
format	Thesis
qualification_level	Master's degree
author	Mohammed, Mohammed Isam Eldin Hassan
author_facet	Mohammed, Mohammed Isam Eldin Hassan
author_sort	Mohammed, Mohammed Isam Eldin Hassan
title	Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
title_short	Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
title_full	Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
title_fullStr	Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
title_full_unstemmed	Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
title_sort	field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2020
url	http://eprints.utm.my/id/eprint/92997/1/MohammedIsamEldinMSKE2020.pdf
_version_	1747818622822121472

Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller

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