Hardware acceleration of secure hash algorithm 3

Secure Hash Algorithm-3 (SHA-3) is the most recent and efficient cryptography hash functions widely used in most information security applications. Contemporary, SHA-3 were built as software where the performance of the cryptographic function is based on the performance of the general-purpose CPU. S...

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Main Author:	Ng, Lai Boon
Format:	Thesis
Language:	English
Published:	2020
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/93016/1/NgLaiBoonMSKE2020.pdf
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id	my-utm-ep.93016
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spelling	my-utm-ep.930162021-11-07T06:00:28Z Hardware acceleration of secure hash algorithm 3 2020 Ng, Lai Boon TK Electrical engineering. Electronics Nuclear engineering Secure Hash Algorithm-3 (SHA-3) is the most recent and efficient cryptography hash functions widely used in most information security applications. Contemporary, SHA-3 were built as software where the performance of the cryptographic function is based on the performance of the general-purpose CPU. Since SHA-3 is frequently used in requires multiple operations per data input and is generally inefficient running on a general-purpose CPU. To improve the performance of the SHA-3 function on data encryption progress, an alternative solution is to implement the SHA-3 algorithm as a hardware accelerator. The proposed accelerator is targeted at the most computation-intensive function in the C-based SHA-3 algorithm which is Keccakf that is executed 97.56% in an SHA-3 operation and synthesized using Xilinx’s Vivado High-Level Synthesis (HLS) to hardware implementations targeted for FPGAs. Besides, the proposed SHA-3 accelerator is employed in the architectural optimization approaches based on the concepts of loop pipelining, loop unrolling, and memory array mapping. Considering the trade-offs between the performance and hardware cost, the SHA-3 architecture in terms of the high throughput and less resource is identified. Incorporated with four-stage sub-pipelining and fully loop unrolling on five permutation steps, followed by memory array partitioning by factor of 25, new SHA-3 hardware architecture is proposed. The proposed SHA-3 accelerator is able to achieve up to 47.7Gbps throughput and operate up to 722.5 MHz. As compared to other existing works, the proposed SHA-3 implementation achieves high throughput performance and operation frequency at a reasonable cost. 2020 Thesis http://eprints.utm.my/id/eprint/93016/ http://eprints.utm.my/id/eprint/93016/1/NgLaiBoonMSKE2020.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135872 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Ng, Lai Boon Hardware acceleration of secure hash algorithm 3
description	Secure Hash Algorithm-3 (SHA-3) is the most recent and efficient cryptography hash functions widely used in most information security applications. Contemporary, SHA-3 were built as software where the performance of the cryptographic function is based on the performance of the general-purpose CPU. Since SHA-3 is frequently used in requires multiple operations per data input and is generally inefficient running on a general-purpose CPU. To improve the performance of the SHA-3 function on data encryption progress, an alternative solution is to implement the SHA-3 algorithm as a hardware accelerator. The proposed accelerator is targeted at the most computation-intensive function in the C-based SHA-3 algorithm which is Keccakf that is executed 97.56% in an SHA-3 operation and synthesized using Xilinx’s Vivado High-Level Synthesis (HLS) to hardware implementations targeted for FPGAs. Besides, the proposed SHA-3 accelerator is employed in the architectural optimization approaches based on the concepts of loop pipelining, loop unrolling, and memory array mapping. Considering the trade-offs between the performance and hardware cost, the SHA-3 architecture in terms of the high throughput and less resource is identified. Incorporated with four-stage sub-pipelining and fully loop unrolling on five permutation steps, followed by memory array partitioning by factor of 25, new SHA-3 hardware architecture is proposed. The proposed SHA-3 accelerator is able to achieve up to 47.7Gbps throughput and operate up to 722.5 MHz. As compared to other existing works, the proposed SHA-3 implementation achieves high throughput performance and operation frequency at a reasonable cost.
format	Thesis
qualification_level	Master's degree
author	Ng, Lai Boon
author_facet	Ng, Lai Boon
author_sort	Ng, Lai Boon
title	Hardware acceleration of secure hash algorithm 3
title_short	Hardware acceleration of secure hash algorithm 3
title_full	Hardware acceleration of secure hash algorithm 3
title_fullStr	Hardware acceleration of secure hash algorithm 3
title_full_unstemmed	Hardware acceleration of secure hash algorithm 3
title_sort	hardware acceleration of secure hash algorithm 3
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2020
url	http://eprints.utm.my/id/eprint/93016/1/NgLaiBoonMSKE2020.pdf
_version_	1747818627483041792

Hardware acceleration of secure hash algorithm 3

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