$FPGA-based design of a math co-processor for the Amir CPU$

FPGA-based design of a math co-processor for the Amir CPU

Math coprocessors are vital components in modern computing to improve the overall performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can only handle integer numbers making it inadequate for high-performance real-time systems. The aim of this project is to design and deve...

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Main Author:	Tan, Arthur Foo Yen
Format:	Thesis
Language:	English
Published:	2020
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/93024/1/TanFooYenMSKE2020.pdf
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id	my-utm-ep.93024
record_format	uketd_dc
spelling	my-utm-ep.930242021-11-07T06:00:32Z FPGA-based design of a math co-processor for the Amir CPU 2020 Tan, Arthur Foo Yen TK Electrical engineering. Electronics Nuclear engineering Math coprocessors are vital components in modern computing to improve the overall performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can only handle integer numbers making it inadequate for high-performance real-time systems. The aim of this project is to design and develop a math coprocessor for the AMIR CPU that can perform addition, subtraction, multiplication and division on IEEE-754 single precision floating-point numbers. The design of the math coprocessor is devised and improved based on past works on IEEE 754 floating-point operations and math coprocessor implementations. The architecture of the proposed math coprocessor consists of a control unit with instruction decode, floating-point computation unit and a register file. The architecture type is a serial controller with pipelined data path. The proposed math coprocessor retrieves instruction from the instruction register, decodes it, retrieves operands from the CPU register, performs computation then stores the results into the internal register, pending retrieval from the AMIR CPU. The proposed math coprocessor managed to achieve at least 99.999% accuracy for all four arithmetic operations with a maximum frequency of 63.8 MHz, while utilizing less than 30% of the available resource on board an Intel Cyclone IV EP4CE10E22C8 FPGA. The design is not without flaws as the proposed design has problems with instruction queueing due to the absence of an instruction buffer. Nevertheless, with further improvements and features, the proposed math coprocessor has the potential to enable the AMIR CPU to be used in a wide range of applications. 2020 Thesis http://eprints.utm.my/id/eprint/93024/ http://eprints.utm.my/id/eprint/93024/1/TanFooYenMSKE2020.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135942 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Tan, Arthur Foo Yen FPGA-based design of a math co-processor for the Amir CPU
description	Math coprocessors are vital components in modern computing to improve the overall performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can only handle integer numbers making it inadequate for high-performance real-time systems. The aim of this project is to design and develop a math coprocessor for the AMIR CPU that can perform addition, subtraction, multiplication and division on IEEE-754 single precision floating-point numbers. The design of the math coprocessor is devised and improved based on past works on IEEE 754 floating-point operations and math coprocessor implementations. The architecture of the proposed math coprocessor consists of a control unit with instruction decode, floating-point computation unit and a register file. The architecture type is a serial controller with pipelined data path. The proposed math coprocessor retrieves instruction from the instruction register, decodes it, retrieves operands from the CPU register, performs computation then stores the results into the internal register, pending retrieval from the AMIR CPU. The proposed math coprocessor managed to achieve at least 99.999% accuracy for all four arithmetic operations with a maximum frequency of 63.8 MHz, while utilizing less than 30% of the available resource on board an Intel Cyclone IV EP4CE10E22C8 FPGA. The design is not without flaws as the proposed design has problems with instruction queueing due to the absence of an instruction buffer. Nevertheless, with further improvements and features, the proposed math coprocessor has the potential to enable the AMIR CPU to be used in a wide range of applications.
format	Thesis
qualification_level	Master's degree
author	Tan, Arthur Foo Yen
author_facet	Tan, Arthur Foo Yen
author_sort	Tan, Arthur Foo Yen
title	FPGA-based design of a math co-processor for the Amir CPU
title_short	FPGA-based design of a math co-processor for the Amir CPU
title_full	FPGA-based design of a math co-processor for the Amir CPU
title_fullStr	FPGA-based design of a math co-processor for the Amir CPU
title_full_unstemmed	FPGA-based design of a math co-processor for the Amir CPU
title_sort	fpga-based design of a math co-processor for the amir cpu
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2020
url	http://eprints.utm.my/id/eprint/93024/1/TanFooYenMSKE2020.pdf
_version_	1747818629464850432

FPGA-based design of a math co-processor for the Amir CPU

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