Hardware accelerator implementation of colour correction algorithm
Colour correction algorithm plays an essential part in processing the colour information. Researches on various statistical methods in colour correction algorithms keep growing in order to obtain higher accuracy and reproducibility for the intended usage. Among those, Polynomial Colour Correction is...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2020
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/93121/1/LohShuTingMSKE2020.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Colour correction algorithm plays an essential part in processing the colour information. Researches on various statistical methods in colour correction algorithms keep growing in order to obtain higher accuracy and reproducibility for the intended usage. Among those, Polynomial Colour Correction is one of the common applications in practice. Nevertheless, the intensive computation and inconvenience of implementing complex algorithm using Hardware Description Language have significant impact on the timing performance especially for those urgent life-threatening diagnosis application. Through this project, a hardware accelerator is proposed to improve the timing performance of the repetitive nature in the Polynomial algorithm while maintaining its accuracy with a minimal degradation. But before designing the hardware accelerator, there is a need to investigate on the compute intensive part of the baseline algorithm. High Level Synthesis tool is used to maximize the design space exploration and effectively minimize the design time. The proposed work has included several optimization techniques such as loop unrolling, pipelining and array partitioning to further exploit the parallelism of the colour correction algorithm. Analysis on latency, total execution time, resource utilization, maximum operating frequency and accuracy with respect to software baseline is conducted to evaluate the outcome of the hardware design. At the end of the project, it is identified that the combination of all the three approaches is able to achieve the highest timing speedup of 22.05 times but at a cost of hardware resources. On the other point of view, it provides several solutions for designs with different usage and targets to achieve based on the performance and hardware cost trade-off. |
|---|