Performance evaluation of finfet silicide based contact through electrical simulation
Continues scaling of device dimension allows the complex integration of increasing number of transistors in a single chip possible. As the semiconductor industry move according to Moore’s law, the scaling down of field effect transistor (FET) has reached less than 10 nm. The conventional planar FET...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2021
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| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/96835/1/AdliaAiniMSKE2021.pdf.pdf |
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| 總結: | Continues scaling of device dimension allows the complex integration of increasing number of transistors in a single chip possible. As the semiconductor industry move according to Moore’s law, the scaling down of field effect transistor (FET) has reached less than 10 nm. The conventional planar FET structure can no longer withstand the short channel effect that become pronounce at ultra-narrow channel length. Therefore, alternative transistor architecture FinFET had been introduced. However, the focus to obtain minimal device leakage from this structure is still on-going due to the thin width of fin that causing an incease in parasitic resistance. In this study, silicidation will be implemented on 10nm FinFET structure and analysed through electrical simulations. The parameters studied in this research are threshold voltage (Vth), off current (Ioff), saturation current (Isat), subthreshold slope (SS) and resistance out (Rout). The silicidation process will involve using following materials which are Silicide, Cobalt Silicide, Nickel Silicide, TiSilicide and Tungsten Silicide. Results from the simulations founds that device power leakage reduced by almost 24% when implemented with Nickle Silicde layer. Futher optimization and simulations will provide insight for engineer in implementing silicidation in short channel devices. |
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