Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust

The goal of trusted computing is to guarantee the behaviour of the software running on the devices. Memory Protection Unit (MPU) secures accesses between main memory, and caches which plays an important role in the System-on-Chip Root-of-Trust. There are several cipher algorithms such as SIMON, PRES...

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Main Author:	Zainurin, Siti Nadhirah
Format:	Thesis
Language:	English
Published:	2021
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/96869/1/SitiNadhirahZainurinMSKE2021.pdf.pdf
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id	my-utm-ep.96869
record_format	uketd_dc
spelling	my-utm-ep.968692022-08-28T03:17:02Z Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust 2021 Zainurin, Siti Nadhirah TK Electrical engineering. Electronics Nuclear engineering The goal of trusted computing is to guarantee the behaviour of the software running on the devices. Memory Protection Unit (MPU) secures accesses between main memory, and caches which plays an important role in the System-on-Chip Root-of-Trust. There are several cipher algorithms such as SIMON, PRESENT, PRINCE, SPECK, and KATAN are suitable for MPU. These ciphers have been analyzed in different metrics such as area, power, throughput, latency, and others. Latency is one of the critical parameters that need to be considered when selecting the MPU cipher. The PRINCE algorithm has the lowest latency based on previous studies to fulfill the main MPU design requirement. The objective of this research is to synthesize and implement the PRINCE cipher architecture for the MPU to secure sensitive data exchange with an emphasis on low latency. For the hardware-based memory protection targeted for Field Programmable Gate Array (FPGA), the PRINCE cipher using three pipeline stage is designed at the register transfer level (RTL) using Verilog and verified by dynamic simulation using the Xillinx ISE. As the additional MPU structure between the main memory and cache increased the memory access latency, we validate the latency result based on memory performance model to quantify the overall performance with the additional five clock cycle encryption latency. The validation result for libquantum and gcc application showed 0.64% and 0.29% execution time overhead due to increased memory, respectively. Besides, the resource overhead decreased as pipeline design was implemented. The impact of additional latency cipher on the execution time has low significant on the overall performance and produced more impact if the Last Level Cache (LLC) miss ratio is high as libquantum application has higher LLC miss ratio compared to gcc application. 2021 Thesis http://eprints.utm.my/id/eprint/96869/ http://eprints.utm.my/id/eprint/96869/1/SitiNadhirahZainurinMSKE2021.pdf.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:142173 masters Universiti Teknologi Malaysia Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Zainurin, Siti Nadhirah Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
description	The goal of trusted computing is to guarantee the behaviour of the software running on the devices. Memory Protection Unit (MPU) secures accesses between main memory, and caches which plays an important role in the System-on-Chip Root-of-Trust. There are several cipher algorithms such as SIMON, PRESENT, PRINCE, SPECK, and KATAN are suitable for MPU. These ciphers have been analyzed in different metrics such as area, power, throughput, latency, and others. Latency is one of the critical parameters that need to be considered when selecting the MPU cipher. The PRINCE algorithm has the lowest latency based on previous studies to fulfill the main MPU design requirement. The objective of this research is to synthesize and implement the PRINCE cipher architecture for the MPU to secure sensitive data exchange with an emphasis on low latency. For the hardware-based memory protection targeted for Field Programmable Gate Array (FPGA), the PRINCE cipher using three pipeline stage is designed at the register transfer level (RTL) using Verilog and verified by dynamic simulation using the Xillinx ISE. As the additional MPU structure between the main memory and cache increased the memory access latency, we validate the latency result based on memory performance model to quantify the overall performance with the additional five clock cycle encryption latency. The validation result for libquantum and gcc application showed 0.64% and 0.29% execution time overhead due to increased memory, respectively. Besides, the resource overhead decreased as pipeline design was implemented. The impact of additional latency cipher on the execution time has low significant on the overall performance and produced more impact if the Last Level Cache (LLC) miss ratio is high as libquantum application has higher LLC miss ratio compared to gcc application.
format	Thesis
qualification_level	Master's degree
author	Zainurin, Siti Nadhirah
author_facet	Zainurin, Siti Nadhirah
author_sort	Zainurin, Siti Nadhirah
title	Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
title_short	Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
title_full	Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
title_fullStr	Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
title_full_unstemmed	Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
title_sort	low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust
granting_institution	Universiti Teknologi Malaysia
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2021
url	http://eprints.utm.my/id/eprint/96869/1/SitiNadhirahZainurinMSKE2021.pdf.pdf
_version_	1747818692781015040

Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust

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