Asic implementation of low latency montgomery modular exponentiation

Nowadays, electronic communication devices tend to design smaller in size, lighter in weight, lower in cost and higher performance. Individual may tend to use electronic communication devices when exchanging sensitive matters, such as personal details, contract documents, company secrets and specifi...

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Main Author:	Liew, Pui Yen
Format:	Thesis
Language:	English
Published:	2022
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/99517/1/LiewPuiYenMSKE2022.pdf
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id	my-utm-ep.99517
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spelling	my-utm-ep.995172023-02-27T08:14:12Z Asic implementation of low latency montgomery modular exponentiation 2022 Liew, Pui Yen TK Electrical engineering. Electronics Nuclear engineering Nowadays, electronic communication devices tend to design smaller in size, lighter in weight, lower in cost and higher performance. Individual may tend to use electronic communication devices when exchanging sensitive matters, such as personal details, contract documents, company secrets and specific passwords are sent to other parties. Since internet is one of the important key contacts and electronically communicates with billions of people, protection for the transmission of important messages over the internet is vital. Encryption plays a vital role for every user in ensuring security of communication within the organization. Hence the algorithms needed for safe communication. The motivation of this project is to protect digital data in computer confidentiality, as it is often stored on computer systems and distributed through the internet or other computer networks. Rivest-Shamir-Adleman algorithm is first introduced by Ron Rivest, Adi Shamir and Leonard Adelman in 1977, and it is known as one of the famous public key cryptography algorithms since it is an asymmetric cryptography. Besides, the theory behind RSA is relatively simple and easy for modification purpose as it relies on algorithm such as factorization and modular exponentiation. In this paper, the whole process and algorithm has been described for 256-bit key size. Due to the bit length of modulus, the work included different but suitable implementation, which is the basic, radix-4 and radix-16 implementations to reduce the speed of cipher-decipher process. Implementation on Verilog HDL using Vivado Design Suite software has been done. Enhancement on speed and delay is the main constraint of this project. According to the synthesis results, the radix-16 Montgomery Multiplier implemented in RSA cipher can be implemented with a nearly 60% reduction in encryption latency. However, radix implementation will involve more loop unrolling steps that resulted in a higher gate count. It is conceivable to absorb the increase in the gate count in the RSA cipher in return for performance as chip technology improves. 2022 Thesis http://eprints.utm.my/id/eprint/99517/ http://eprints.utm.my/id/eprint/99517/1/LiewPuiYenMSKE2022.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149940 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Liew, Pui Yen Asic implementation of low latency montgomery modular exponentiation
description	Nowadays, electronic communication devices tend to design smaller in size, lighter in weight, lower in cost and higher performance. Individual may tend to use electronic communication devices when exchanging sensitive matters, such as personal details, contract documents, company secrets and specific passwords are sent to other parties. Since internet is one of the important key contacts and electronically communicates with billions of people, protection for the transmission of important messages over the internet is vital. Encryption plays a vital role for every user in ensuring security of communication within the organization. Hence the algorithms needed for safe communication. The motivation of this project is to protect digital data in computer confidentiality, as it is often stored on computer systems and distributed through the internet or other computer networks. Rivest-Shamir-Adleman algorithm is first introduced by Ron Rivest, Adi Shamir and Leonard Adelman in 1977, and it is known as one of the famous public key cryptography algorithms since it is an asymmetric cryptography. Besides, the theory behind RSA is relatively simple and easy for modification purpose as it relies on algorithm such as factorization and modular exponentiation. In this paper, the whole process and algorithm has been described for 256-bit key size. Due to the bit length of modulus, the work included different but suitable implementation, which is the basic, radix-4 and radix-16 implementations to reduce the speed of cipher-decipher process. Implementation on Verilog HDL using Vivado Design Suite software has been done. Enhancement on speed and delay is the main constraint of this project. According to the synthesis results, the radix-16 Montgomery Multiplier implemented in RSA cipher can be implemented with a nearly 60% reduction in encryption latency. However, radix implementation will involve more loop unrolling steps that resulted in a higher gate count. It is conceivable to absorb the increase in the gate count in the RSA cipher in return for performance as chip technology improves.
format	Thesis
qualification_level	Master's degree
author	Liew, Pui Yen
author_facet	Liew, Pui Yen
author_sort	Liew, Pui Yen
title	Asic implementation of low latency montgomery modular exponentiation
title_short	Asic implementation of low latency montgomery modular exponentiation
title_full	Asic implementation of low latency montgomery modular exponentiation
title_fullStr	Asic implementation of low latency montgomery modular exponentiation
title_full_unstemmed	Asic implementation of low latency montgomery modular exponentiation
title_sort	asic implementation of low latency montgomery modular exponentiation
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2022
url	http://eprints.utm.my/id/eprint/99517/1/LiewPuiYenMSKE2022.pdf
_version_	1776100609866334208

Asic implementation of low latency montgomery modular exponentiation

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